DocumentHdrVersion "1.1"
Header (DocumentHdr
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
itemName "ALL"
)
(DmPackageRef
library "ieee"
unitName "std_logic_arith"
itemName "ALL"
)
]
libraryRefs [
"ieee"
]
)
version "20.1"
appVersion "2004.1a (Build 15)"
model (Symbol
commonDM (CommonDM
ldm (LogicalDM
suid 15,0
emptyRow *1 (LEmptyRow
)
uid 158,0
optionalChildren [
*2 (RefLabelRowHdr
)
*3 (TitleRowHdr
)
*4 (FilterRowHdr
)
*5 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*6 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*7 (GroupColHdr
tm "GroupColHdrMgr"
)
*8 (NameColHdr
tm "NameColHdrMgr"
)
*9 (ModeColHdr
tm "ModeColHdrMgr"
)
*10 (TypeColHdr
tm "TypeColHdrMgr"
)
*11 (BoundsColHdr
tm "BoundsColHdrMgr"
)
*12 (InitColHdr
tm "InitColHdrMgr"
)
*13 (EolColHdr
tm "EolColHdrMgr"
)
*14 (LogPort
port (LogicalPort
m 1
decl (Decl
n "ADR1"
t "std_logic"
o 8
suid 1,0
)
)
uid 126,0
)
*15 (LogPort
port (LogicalPort
m 1
decl (Decl
n "ADR2"
t "std_logic"
o 9
suid 2,0
)
)
uid 128,0
)
*16 (LogPort
port (LogicalPort
m 1
decl (Decl
n "ADR3"
t "std_logic"
o 10
suid 3,0
)
)
uid 130,0
)
*17 (LogPort
port (LogicalPort
decl (Decl
n "BCS9_n"
t "std_logic"
o 1
suid 4,0
)
)
uid 132,0
)
*18 (LogPort
port (LogicalPort
m 1
decl (Decl
n "CLK"
t "std_logic"
o 14
suid 5,0
)
)
uid 134,0
)
*19 (LogPort
port (LogicalPort
m 1
decl (Decl
n "CS9_n"
t "std_logic"
o 11
suid 6,0
)
)
uid 136,0
)
*20 (LogPort
port (LogicalPort
decl (Decl
n "DSACK1_n"
t "std_logic"
o 12
suid 7,0
)
)
uid 138,0
)
*21 (LogPort
port (LogicalPort
decl (Decl
n "HCNTL0_DSP"
t "std_logic"
o 2
suid 8,0
)
)
uid 140,0
)
*22 (LogPort
port (LogicalPort
decl (Decl
n "HCNTL1_DSP"
t "std_logic"
o 3
suid 9,0
)
)
uid 142,0
)
*23 (LogPort
port (LogicalPort
decl (Decl
n "HHWIL_DSP"
t "std_logic"
o 4
suid 10,0
)
)
uid 144,0
)
*24 (LogPort
port (LogicalPort
m 1
decl (Decl
n "HINT_DSP_n"
t "std_logic"
o 5
suid 11,0
)
)
uid 146,0
)
*25 (LogPort
port (LogicalPort
m 1
decl (Decl
n "HRDY_DSP_n"
t "std_logic"
o 6
suid 12,0
)
)
uid 148,0
)
*26 (LogPort
port (LogicalPort
decl (Decl
n "IRQ5_n"
t "std_logic"
o 13
suid 13,0
)
)
uid 150,0
)
*27 (LogPort
port (LogicalPort
m 1
decl (Decl
n "R_W"
t "std_logic"
o 15
suid 14,0
)
)
uid 152,0
)
*28 (LogPort
port (LogicalPort
decl (Decl
n "TP"
t "std_logic"
o 7
suid 15,0
)
)
uid 154,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 171,0
optionalChildren [
*29 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *30 (MRCItem
litem &1
pos 3
dimension 20
)
uid 173,0
optionalChildren [
*31 (MRCItem
litem &2
pos 0
dimension 20
uid 174,0
)
*32 (MRCItem
litem &3
pos 1
dimension 23
uid 175,0
)
*33 (MRCItem
litem &4
pos 2
hidden 1
dimension 20
uid 176,0
)
*34 (MRCItem
litem &14
pos 0
dimension 20
uid 127,0
)
*35 (MRCItem
litem &15
pos 1
dimension 20
uid 129,0
)
*36 (MRCItem
litem &16
pos 2
dimension 20
uid 131,0
)
*37 (MRCItem
litem &17
pos 3
dimension 20
uid 133,0
)
*38 (MRCItem
litem &18
pos 4
dimension 20
uid 135,0
)
*39 (MRCItem
litem &19
pos 5
dimension 20
uid 137,0
)
*40 (MRCItem
litem &20
pos 6
dimension 20
uid 139,0
)
*41 (MRCItem
litem &21
pos 7
dimension 20
uid 141,0
)
*42 (MRCItem
litem &22
pos 8
dimension 20
uid 143,0
)
*43 (MRCItem
litem &23
pos 9
dimension 20
uid 145,0
)
*44 (MRCItem
litem &24
pos 10
dimension 20
uid 147,0
)
*45 (MRCItem
litem &25
pos 11
dimension 20
uid 149,0
)
*46 (MRCItem
litem &26
pos 12
dimension 20
uid 151,0
)
*47 (MRCItem
litem &27
pos 13
dimension 20
uid 153,0
)
*48 (MRCItem
litem &28
pos 14
dimension 20
uid 155,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 177,0
optionalChildren [
*49 (MRCItem
litem &5
pos 0
dimension 20
uid 178,0
)
*50 (MRCItem
litem &7
pos 1
dimension 50
uid 179,0
)
*51 (MRCItem
litem &8
pos 2
dimension 100
uid 180,0
)
*52 (MRCItem
litem &9
pos 3
dimension 50
uid 181,0
)
*53 (MRCItem
litem &10
pos 4
dimension 100
uid 182,0
)
*54 (MRCItem
litem &11
pos 5
dimension 100
uid 183,0
)
*55 (MRCItem
litem &12
pos 6
dimension 50
uid 184,0
)
*56 (MRCItem
litem &13
pos 7
dimension 80
uid 185,0
)
]
)
fixedCol 4
fixedRow 2
name "Ports"
uid 172,0
vaOverrides [
]
)
]
)
uid 157,0
)
VExpander (VariableExpander
vvMap [
(vvPair
variable "HDLDir"
value "C:\\hds_projects\\2998_Per_FPGA_RevC_Ver50\\361000242_RevA\\PERSONALITY_FPGA\\hdl"
)
(vvPair
variable "HDSDir"
value "C:\\hds_projects\\2998_Per_FPGA_RevC_Ver50\\361000242_RevA\\PERSONALITY_FPGA\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "C:\\hds_projects\\2998_Per_FPGA_RevC_Ver50\\361000242_RevA\\PERSONALITY_FPGA\\hds\\@h@o@s@t@p@o@r@t_tester\\interface.info"
)
(vvPair
variable "SideDataUserDir"
value "C:\\hds_projects\\2998_Per_FPGA_RevC_Ver50\\361000242_RevA\\PERSONALITY_FPGA\\hds\\@h@o@s@t@p@o@r@t_tester\\interface.user"
)
(vvPair
variable "SourceDir"
value "C:\\hds_projects\\2998_Per_FPGA_RevC_Ver50\\361000242_RevA\\PERSONALITY_FPGA\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "interface"
)
(vvPair
variable "config"
value "%(unit)_config"
)
(vvPair
variable "d"
value "C:\\hds_projects\\2998_Per_FPGA_RevC_Ver50\\361000242_RevA\\PERSONALITY_FPGA\\hds\\@h@o@s@t@p@o@r@t_tester"
)
(vvPair
variable "d_logical"
value "C:\\hds_projects\\2998_Per_FPGA_RevC_Ver50\\361000242_RevA\\PERSONALITY_FPGA\\hds\\HOSTPORT_tester"
)
(vvPair
variable "date"
value "10/09/2006"
)
(vvPair
variable "day"
value "Mon"
)
(vvPair
variable "day_long"
value "Monday"
)
(vvPair
variable "dd"
value "09"
)
(vvPair
variable "entity_name"
value "HOSTPORT_tester"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "interface"
)
(vvPair
variable "f_logical"
value "interface"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "DEARY-JUSTIN"
)
(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "PERSONALITY_FPGA"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$HDS_PROJECT_DIR/PLD_2998_lib/work/"
)
(vvPair
variable "library_downstream_SpectrumDataPrep"
value "$HDS_PROJECT_DIR/PLD_2998_lib/ls/"
)
(vvPair
variable "mm"
value "10"
)
(vvPair
variable "module_name"
value "HOSTPORT_tester"
)
(vvPair
variable "month"
value "Oct"
)
(vvPair
variable "month_long"
value "October"
)
(vvPair
variable "p"
value "C:\\hds_projects\\2998_Per_FPGA_RevC_Ver50\\361000242_RevA\\PERSONALITY_FPGA\\hds\\@h@o@s@t@p@o@r@t_tester\\interface"
)
(vvPair
variable "p_logical"
value "C:\\hds_projects\\2998_Per_FPGA_RevC_Ver50\\361000242_RevA\\PERSONALITY_FPGA\\hds\\HOSTPORT_tester\\interface"
)
(vvPair
variable "project_name"
value "PLD_2998"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_ADMS"
value "<TBD>"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_LeonardoPath"
value "$HDS_HOME/../Exemplar/bin/win32"
)
(vvPair
variable "task_ModelSimPath"
value "$HDS_HOME/../Modeltech/win32"
)
(vvPair
variable "task_NC"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "time"
value "09:09:54"
)
(vvPair
variable "unit"
value "HOSTPORT_tester"
)
(vvPair
variable "user"
value "DearyJ"
)
(vvPair
variable "version"
value "2004.1a (Build 15)"
)
(vvPair
variable "view"
value "interface"
)
(vvPair
variable "year"
value "2006"
)
(vvPair
variable "yy"
value "06"
)
]
)
uid 156,0
optionalChildren [
*57 (SymbolBody
uid 8,0
optionalChildren [
*58 (CptPort
uid 51,0
ps "OnEdgeStrategy"
shape (Triangle
uid 52,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,6625,15000,7375"
)
tg (CPTG
uid 53,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 54,0
va (VaSet
)
xt "16000,6350,19300,7650"
st "ADR1"
blo "16000,7350"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 55,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,8000,61500,8800"
st "ADR1       : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "ADR1"
t "std_logic"
o 8
suid 1,0
)
)
)
*59 (CptPort
uid 56,0
ps "OnEdgeStrategy"
shape (Triangle
uid 57,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,7625,15000,8375"
)
tg (CPTG
uid 58,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 59,0
va (VaSet
)
xt "16000,7350,19300,8650"
st "ADR2"
blo "16000,8350"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 60,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,8800,61500,9600"
st "ADR2       : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "ADR2"
t "std_logic"
o 9
suid 2,0
)
)
)
*60 (CptPort
uid 61,0
ps "OnEdgeStrategy"
shape (Triangle
uid 62,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,8625,15000,9375"
)
tg (CPTG
uid 63,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 64,0
va (VaSet
)
xt "16000,8350,19300,9650"
st "ADR3"
blo "16000,9350"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 65,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,9600,61500,10400"
st "ADR3       : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "ADR3"
t "std_logic"
o 10
suid 3,0
)
)
)
*61 (CptPort
uid 66,0
ps "OnEdgeStrategy"
shape (Triangle
uid 67,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "32000,15625,32750,16375"
)
tg (CPTG
uid 68,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 69,0
va (VaSet
)
xt "26500,15350,31000,16650"
st "BCS9_n"
ju 2
blo "31000,16350"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 70,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,2400,61500,3200"
st "BCS9_n     : IN     std_logic  ;"
)
thePort (LogicalPort
decl (Decl
n "BCS9_n"
t "std_logic"
o 1
suid 4,0
)
)
)
*62 (CptPort
uid 71,0
ps "OnEdgeStrategy"
shape (Triangle
uid 72,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,16625,15000,17375"
)
tg (CPTG
uid 73,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 74,0
va (VaSet
)
xt "16000,16350,18600,17650"
st "CLK"
blo "16000,17350"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 75,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,10400,61500,11200"
st "CLK        : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "CLK"
t "std_logic"
o 14
suid 5,0
)
)
)
*63 (CptPort
uid 76,0
ps "OnEdgeStrategy"
shape (Triangle
uid 77,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,14625,15000,15375"
)
tg (CPTG
uid 78,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 79,0
va (VaSet
)
xt "16000,14350,19800,15650"
st "CS9_n"
blo "16000,15350"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 80,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,11200,61500,12000"
st "CS9_n      : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "CS9_n"
t "std_logic"
o 11
suid 6,0
)
)
)
*64 (CptPort
uid 81,0
ps "OnEdgeStrategy"
shape (Triangle
uid 82,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,12625,15000,13375"
)
tg (CPTG
uid 83,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 84,0
va (VaSet
)
xt "16000,12350,21900,13650"
st "DSACK1_n"
blo "16000,13350"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 85,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,3200,61500,4000"
st "DSACK1_n   : IN     std_logic  ;"
)
thePort (LogicalPort
decl (Decl
n "DSACK1_n"
t "std_logic"
o 12
suid 7,0
)
)
)
*65 (CptPort
uid 86,0
ps "OnEdgeStrategy"
shape (Triangle
uid 87,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "32000,7625,32750,8375"
)
tg (CPTG
uid 88,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 89,0
va (VaSet
)
xt "23100,7350,31000,8650"
st "HCNTL0_DSP"
ju 2
blo "31000,8350"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 90,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,4000,61500,4800"
st "HCNTL0_DSP : IN     std_logic  ;"
)
thePort (LogicalPort
decl (Decl
n "HCNTL0_DSP"
t "std_logic"
o 2
suid 8,0
)
)
)
*66 (CptPort
uid 91,0
ps "OnEdgeStrategy"
shape (Triangle
uid 92,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "32000,8625,32750,9375"
)
tg (CPTG
uid 93,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 94,0
va (VaSet
)
xt "23100,8350,31000,9650"
st "HCNTL1_DSP"
ju 2
blo "31000,9350"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 95,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,4800,61500,5600"
st "HCNTL1_DSP : IN     std_logic  ;"
)
thePort (LogicalPort
decl (Decl
n "HCNTL1_DSP"
t "std_logic"
o 3
suid 9,0
)
)
)
*67 (CptPort
uid 96,0
ps "OnEdgeStrategy"
shape (Triangle
uid 97,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "32000,6625,32750,7375"
)
tg (CPTG
uid 98,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 99,0
va (VaSet
)
xt "24500,6350,31000,7650"
st "HHWIL_DSP"
ju 2
blo "31000,7350"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 100,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,5600,61500,6400"
st "HHWIL_DSP  : IN     std_logic  ;"
)
thePort (LogicalPort
decl (Decl
n "HHWIL_DSP"
t "std_logic"
o 4
suid 10,0
)
)
)
*68 (CptPort
uid 101,0
ps "OnEdgeStrategy"
shape (Triangle
uid 102,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "32000,10625,32750,11375"
)
tg (CPTG
uid 103,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 104,0
va (VaSet
)
xt "23500,10350,31000,11650"
st "HINT_DSP_n"
ju 2
blo "31000,11350"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 105,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,12000,61500,12800"
st "HINT_DSP_n : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "HINT_DSP_n"
t "std_logic"
o 5
suid 11,0
)
)
)
*69 (CptPort
uid 106,0
ps "OnEdgeStrategy"
shape (Triangle
uid 107,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "32000,12625,32750,13375"
)
tg (CPTG
uid 108,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 109,0
va (VaSet
)
xt "23100,12350,31000,13650"
st "HRDY_DSP_n"
ju 2
blo "31000,13350"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 110,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,12800,61500,13600"
st "HRDY_DSP_n : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "HRDY_DSP_n"
t "std_logic"
o 6
suid 12,0
)
)
)
*70 (CptPort
uid 111,0
ps "OnEdgeStrategy"
shape (Triangle
uid 112,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,10625,15000,11375"
)
tg (CPTG
uid 113,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 114,0
va (VaSet
)
xt "16000,10350,20200,11650"
st "IRQ5_n"
blo "16000,11350"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 115,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,6400,61500,7200"
st "IRQ5_n     : IN     std_logic  ;"
)
thePort (LogicalPort
decl (Decl
n "IRQ5_n"
t "std_logic"
o 13
suid 13,0
)
)
)
*71 (CptPort
uid 116,0
ps "OnEdgeStrategy"
shape (Triangle
uid 117,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,17625,15000,18375"
)
tg (CPTG
uid 118,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 119,0
va (VaSet
)
xt "16000,17350,18800,18650"
st "R_W"
blo "16000,18350"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 120,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,13600,60500,14400"
st "R_W        : OUT    std_logic "
)
thePort (LogicalPort
m 1
decl (Decl
n "R_W"
t "std_logic"
o 15
suid 14,0
)
)
)
*72 (CptPort
uid 121,0
ps "OnEdgeStrategy"
shape (Triangle
uid 122,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "32000,17625,32750,18375"
)
tg (CPTG
uid 123,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 124,0
va (VaSet
)
xt "29000,17350,31000,18650"
st "TP"
ju 2
blo "31000,18350"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 125,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,7200,61500,8000"
st "TP         : IN     std_logic  ;"
)
thePort (LogicalPort
decl (Decl
n "TP"
t "std_logic"
o 7
suid 15,0
)
)
)
]
shape (Rectangle
uid 9,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "15000,6000,32000,20000"
)
biTextGroup (BiTextGroup
uid 10,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
first (Text
uid 11,0
va (VaSet
font "Arial,12,1"
)
xt "17550,11500,30650,13000"
st "PERSONALITY_FPGA"
blo "17550,12700"
)
second (Text
uid 12,0
va (VaSet
font "Arial,12,1"
)
xt "17550,13000,29450,14500"
st "HOSTPORT_tester"
blo "17550,14200"
)
)
gi *73 (GenericInterface
uid 13,0
ps "CenterOffsetStrategy"
matrix (Matrix
uid 14,0
text (MLText
uid 15,0
va (VaSet
font "Courier New,10,0"
)
xt "-3500,9000,10300,10200"
st "Generic Declarations"
)
header "Generic Declarations"
showHdrWhenContentsEmpty 1
)
elements [
]
)
portInstanceVisAsIs 1
portInstanceVis (PortSigDisplay
sTC 0
sF 0
)
portVis (PortSigDisplay
sTC 0
sF 0
)
)
*74 (Grouping
uid 16,0
optionalChildren [
*75 (CommentText
uid 18,0
shape (Rectangle
uid 19,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "31000,50000,48000,51000"
)
oxt "18000,70000,35000,71000"
text (MLText
uid 20,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "31200,50000,40900,51000"
st "
by %user on %dd %month %year
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
titleBlock 1
)
*76 (CommentText
uid 21,0
shape (Rectangle
uid 22,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "48000,46000,52000,47000"
)
oxt "35000,66000,39000,67000"
text (MLText
uid 23,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "48200,46000,51200,47000"
st "
Project:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*77 (CommentText
uid 24,0
shape (Rectangle
uid 25,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "31000,48000,48000,49000"
)
oxt "18000,68000,35000,69000"
text (MLText
uid 26,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "31200,48000,41200,49000"
st "
<enter diagram title here>
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
titleBlock 1
)
*78 (CommentText
uid 27,0
shape (Rectangle
uid 28,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "27000,48000,31000,49000"
)
oxt "14000,68000,18000,69000"
text (MLText
uid 29,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "27200,48000,29300,49000"
st "
Title:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*79 (CommentText
uid 30,0
shape (Rectangle
uid 31,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "48000,47000,68000,51000"
)
oxt "35000,67000,55000,71000"
text (MLText
uid 32,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "48200,47200,57400,48200"
st "
<enter comments here>
"
tm "CommentText"
wrapOption 3
visibleHeight 4000
visibleWidth 20000
)
ignorePrefs 1
titleBlock 1
)
*80 (CommentText
uid 33,0
shape (Rectangle
uid 34,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "52000,46000,68000,47000"
)
oxt "39000,66000,55000,67000"
text (MLText
uid 35,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "52200,46000,56100,47000"
st "
%project_name
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 16000
)
position 1
ignorePrefs 1
titleBlock 1
)
*81 (CommentText
uid 36,0
shape (Rectangle
uid 37,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "27000,46000,48000,48000"
)
oxt "14000,66000,35000,68000"
text (MLText
uid 38,0
va (VaSet
fg "32768,0,0"
)
xt "32650,46350,42350,47650"
st "
<company name>
"
ju 0
tm "CommentText"
wrapOption 3
visibleHeight 2000
visibleWidth 21000
)
position 1
ignorePrefs 1
titleBlock 1
)
*82 (CommentText
uid 39,0
shape (Rectangle
uid 40,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "27000,49000,31000,50000"
)
oxt "14000,69000,18000,70000"
text (MLText
uid 41,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "27200,49000,29300,50000"
st "
Path:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*83 (CommentText
uid 42,0
shape (Rectangle
uid 43,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "27000,50000,31000,51000"
)
oxt "14000,70000,18000,71000"
text (MLText
uid 44,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "27200,50000,29900,51000"
st "
Edited:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*84 (CommentText
uid 45,0
shape (Rectangle
uid 46,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "31000,49000,48000,50000"
)
oxt "18000,69000,35000,70000"
text (MLText
uid 47,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "31200,49000,47100,50000"
st "
%library/%unit/%view
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
titleBlock 1
)
]
shape (GroupingShape
uid 17,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
lineWidth 2
)
xt "27000,46000,68000,51000"
)
oxt "14000,66000,55000,71000"
)
]
LanguageMgr "VhdlLangMgr"
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 1
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *85 (PackageList
uid 48,0
stg "VerticalLayoutStrategy"
textVec [
*86 (Text
uid 49,0
va (VaSet
font "arial,10,1"
)
xt "0,0,7600,1200"
st "Package List"
blo "0,1000"
)
*87 (MLText
uid 50,0
va (VaSet
)
xt "0,1200,16300,5100"
st "LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;"
tm "PackageList"
)
]
)
windowSize "0,0,895,750"
viewArea "0,0,0,0"
cachedDiagramExtent "0,0,0,0"
pageBreakOrigin "0,0"
defaultCommentText (CommentText
shape (Rectangle
layer 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
lineColor "0,0,32768"
)
xt "0,0,15000,5000"
)
text (MLText
va (VaSet
fg "0,0,32768"
)
xt "200,200,2900,1500"
st "
Text
"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
)
defaultPanel (Panel
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "32768,0,0"
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
font "Arial,10,1"
)
xt "1000,1000,5000,2200"
st "Panel0"
blo "1000,2000"
tm "PanelText"
)
)
)
parentGraphicsRef (HdmGraphicsRef
libraryName "PERSONALITY_FPGA"
entityName "HOSTPORT_tb"
viewName "struct.bd"
)
defaultSymbolBody (SymbolBody
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "15000,6000,39000,26000"
)
biTextGroup (BiTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
first (Text
va (VaSet
font "Arial,12,1"
)
xt "24150,14500,29850,16000"
st "<library>"
blo "24150,15700"
)
second (Text
va (VaSet
font "Arial,12,1"
)
xt "24150,16000,28250,17500"
st "<cell>"
blo "24150,17200"
)
)
gi *88 (GenericInterface
ps "CenterOffsetStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,10,0"
)
xt "0,12000,13800,13200"
st "Generic Declarations"
)
header "Generic Declarations"
showHdrWhenContentsEmpty 1
)
elements [
]
)
portInstanceVisAsIs 1
portInstanceVis (PortSigDisplay
sIVOD 1
)
portVis (PortSigDisplay
sIVOD 1
)
)
defaultCptPort (CptPort
ps "OnEdgeStrategy"
shape (Triangle
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,2100,2050"
st "In0"
blo "0,1750"
tm "CptPortNameMgr"
)
)
dt (MLText
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
decl (Decl
n "In0"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 0
)
)
)
defaultCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
bg "0,0,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,4000,2050"
st "Buffer0"
blo "0,1750"
tm "CptPortNameMgr"
)
)
dt (MLText
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
m 3
decl (Decl
n "Buffer0"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 0
)
)
)
DeclarativeBlock *89 (SymDeclBlock
uid 1,0
stg "SymDeclLayoutStrategy"
declLabel (Text
uid 2,0
va (VaSet
font "Arial,10,1"
)
xt "42000,0,49400,1200"
st "Declarations"
blo "42000,1000"
)
portLabel (Text
uid 3,0
va (VaSet
font "Arial,10,1"
)
xt "42000,1200,45500,2400"
st "Ports:"
blo "42000,2200"
)
externalLabel (Text
uid 4,0
va (VaSet
font "Arial,10,1"
)
xt "42000,14400,45200,15600"
st "User:"
blo "42000,15400"
)
internalLabel (Text
uid 6,0
va (VaSet
isHidden 1
font "Arial,10,1"
)
xt "42000,0,49800,1200"
st "Internal User:"
blo "42000,1000"
)
externalText (MLText
uid 5,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,15600,44000,15600"
tm "SyDeclarativeTextMgr"
)
internalText (MLText
uid 7,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "42000,0,42000,0"
tm "SyDeclarativeTextMgr"
)
)
lastUid 197,0
)
