DocumentHdrVersion "1.1"
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unitName "std_logic_1164"
itemName "ALL"
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unitName "std_logic_arith"
itemName "ALL"
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libraryRefs [
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version "20.1"
appVersion "2004.1a (Build 15)"
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value "C:\\hds_projects\\2998_Per_FPGA_RevC_Ver50\\361000242_RevA\\PERSONALITY_FPGA\\hdl"
)
(vvPair
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)
(vvPair
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(vvPair
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value "C:\\hds_projects\\2998_Per_FPGA_RevC_Ver50\\361000242_RevA\\PERSONALITY_FPGA\\hds\\refmachine_tester\\interface.user"
)
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value "HDL Designer"
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(vvPair
variable "arch_name"
value "interface"
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(vvPair
variable "config"
value "%(unit)_config"
)
(vvPair
variable "d"
value "C:\\hds_projects\\2998_Per_FPGA_RevC_Ver50\\361000242_RevA\\PERSONALITY_FPGA\\hds\\refmachine_tester"
)
(vvPair
variable "d_logical"
value "C:\\hds_projects\\2998_Per_FPGA_RevC_Ver50\\361000242_RevA\\PERSONALITY_FPGA\\hds\\refmachine_tester"
)
(vvPair
variable "date"
value "10/09/2006"
)
(vvPair
variable "day"
value "Mon"
)
(vvPair
variable "day_long"
value "Monday"
)
(vvPair
variable "dd"
value "09"
)
(vvPair
variable "entity_name"
value "refmachine_tester"
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variable "ext"
value "<TBD>"
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(vvPair
variable "f"
value "interface"
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(vvPair
variable "f_logical"
value "interface"
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(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "DEARY-JUSTIN"
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(vvPair
variable "language"
value "VHDL"
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(vvPair
variable "library"
value "PERSONALITY_FPGA"
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(vvPair
variable "library_downstream_ModelSimCompiler"
value "$HDS_PROJECT_DIR/PLD_2998_lib/work/"
)
(vvPair
variable "library_downstream_SpectrumDataPrep"
value "$HDS_PROJECT_DIR/PLD_2998_lib/ls/"
)
(vvPair
variable "mm"
value "10"
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(vvPair
variable "module_name"
value "refmachine_tester"
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(vvPair
variable "month"
value "Oct"
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(vvPair
variable "month_long"
value "October"
)
(vvPair
variable "p"
value "C:\\hds_projects\\2998_Per_FPGA_RevC_Ver50\\361000242_RevA\\PERSONALITY_FPGA\\hds\\refmachine_tester\\interface"
)
(vvPair
variable "p_logical"
value "C:\\hds_projects\\2998_Per_FPGA_RevC_Ver50\\361000242_RevA\\PERSONALITY_FPGA\\hds\\refmachine_tester\\interface"
)
(vvPair
variable "project_name"
value "PLD_2998"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_ADMS"
value "<TBD>"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_LeonardoPath"
value "$HDS_HOME/../Exemplar/bin/win32"
)
(vvPair
variable "task_ModelSimPath"
value "$HDS_HOME/../Modeltech/win32"
)
(vvPair
variable "task_NC"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "time"
value "09:09:54"
)
(vvPair
variable "unit"
value "refmachine_tester"
)
(vvPair
variable "user"
value "DearyJ"
)
(vvPair
variable "version"
value "2004.1a (Build 15)"
)
(vvPair
variable "view"
value "interface"
)
(vvPair
variable "year"
value "2006"
)
(vvPair
variable "yy"
value "06"
)
]
)
uid 128,0
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ps "OnEdgeStrategy"
shape (Triangle
uid 2628,0
ro 270
va (VaSet
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fg "0,65535,0"
)
xt "14250,9625,15000,10375"
)
tg (CPTG
uid 2629,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "16000,9350,21400,10650"
st "AD_BUSY"
blo "16000,10350"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2631,0
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font "Courier New,8,0"
)
xt "44000,5600,63000,6400"
st "AD_BUSY       : OUT    STD_LOGIC  ;"
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ps "OnEdgeStrategy"
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xt "33000,8625,33750,9375"
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st "AD_SPI_CS"
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blo "32000,9350"
tm "CptPortNameMgr"
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)
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xt "44000,8800,63000,9600"
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ps "OnEdgeStrategy"
shape (Triangle
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ro 270
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xt "14250,8625,15000,9375"
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st "AD_SPI_DO"
blo "16000,9350"
tm "CptPortNameMgr"
)
)
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uid 2641,0
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)
xt "44000,4800,63000,5600"
st "AD_SPI_DO     : OUT    STD_LOGIC  ;"
)
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m 1
decl (Decl
n "AD_SPI_DO"
t "STD_LOGIC"
o 4
suid 317,0
)
)
)
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ps "OnEdgeStrategy"
shape (Triangle
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ro 270
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uid 2645,0
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xt "23800,7350,32000,8650"
st "AD_SPI_SCLK"
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blo "32000,8350"
tm "CptPortNameMgr"
)
)
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xt "44000,8000,63000,8800"
st "AD_SPI_SCLK   : IN     STD_LOGIC  ;"
)
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decl (Decl
n "AD_SPI_SCLK"
t "STD_LOGIC"
o 8
suid 318,0
)
)
)
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ps "OnEdgeStrategy"
shape (Triangle
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ro 270
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xt "14250,6625,15000,7375"
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tg (CPTG
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blo "16000,7350"
tm "CptPortNameMgr"
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)
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xt "44000,2400,63000,3200"
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ps "OnEdgeStrategy"
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ro 270
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xt "14250,12625,15000,13375"
)
tg (CPTG
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stg "VerticalLayoutStrategy"
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st "DSP_SPI_CS"
blo "16000,13350"
tm "CptPortNameMgr"
)
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xt "44000,7200,63000,8000"
st "DSP_SPI_CS    : OUT    STD_LOGIC  ;"
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shape (Triangle
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xt "33000,9625,33750,10375"
)
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st "DSP_SPI_DI"
ju 2
blo "32000,10350"
tm "CptPortNameMgr"
)
)
dt (MLText
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va (VaSet
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xt "44000,9600,63000,10400"
st "DSP_SPI_DI    : IN     STD_LOGIC  ;"
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decl (Decl
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o 10
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ps "OnEdgeStrategy"
shape (Triangle
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ro 270
va (VaSet
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xt "14250,11625,15000,12375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
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va (VaSet
)
xt "16000,11350,24900,12650"
st "DSP_SPI_SCLK"
blo "16000,12350"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2666,0
va (VaSet
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)
xt "44000,6400,63000,7200"
st "DSP_SPI_SCLK  : OUT    STD_LOGIC  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "DSP_SPI_SCLK"
t "STD_LOGIC"
o 6
suid 322,0
)
)
)
*58 (CptPort
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ps "OnEdgeStrategy"
shape (Triangle
uid 2668,0
ro 270
va (VaSet
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fg "0,65535,0"
)
xt "14250,10625,15000,11375"
)
tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
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va (VaSet
)
xt "16000,10350,26000,11650"
st "REF_START_EXP"
blo "16000,11350"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2671,0
va (VaSet
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)
xt "44000,4000,63000,4800"
st "REF_START_EXP : OUT    STD_LOGIC  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "REF_START_EXP"
t "STD_LOGIC"
o 3
suid 323,0
)
)
)
*59 (CptPort
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ps "OnEdgeStrategy"
shape (Triangle
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ro 270
va (VaSet
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fg "0,65535,0"
)
xt "14250,7625,15000,8375"
)
tg (CPTG
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ps "CptPortTextPlaceStrategy"
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va (VaSet
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xt "16000,7350,20100,8650"
st "RESET"
blo "16000,8350"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2676,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,3200,63000,4000"
st "RESET         : OUT    STD_LOGIC  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "RESET"
t "STD_LOGIC"
o 2
suid 324,0
)
)
)
*60 (CptPort
uid 2677,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2678,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,10625,33750,11375"
)
tg (CPTG
uid 2679,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2680,0
va (VaSet
)
xt "22000,10350,32000,11650"
st "START_REF_DSP"
ju 2
blo "32000,11350"
tm "CptPortNameMgr"
)
)
dt (MLText
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va (VaSet
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)
xt "44000,10400,62000,11200"
st "START_REF_DSP : IN     STD_LOGIC "
)
thePort (LogicalPort
decl (Decl
n "START_REF_DSP"
t "STD_LOGIC"
o 11
suid 325,0
)
)
)
]
shape (Rectangle
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va (VaSet
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fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "15000,6000,33000,15000"
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oxt "15000,6000,33000,14000"
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xt "18000,10500,30000,12000"
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header "Generic Declarations"
showHdrWhenContentsEmpty 1
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elements [
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portInstanceVis (PortSigDisplay
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portVis (PortSigDisplay
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tm "CommentText"
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