Changed By ....................	Justin Deary
Rev............................	5A
QUARTUS PLACE&ROUTE Date ......	1/29/06
New Checksum ..................	0x0000000
DEVICE ........................	EP1K30QC208-3
RBF FILE NAME .................	Classic_2998Ver5A.rbf   


........ RESON FOR CHANGES ........................
ver 40 
  FPGA image is for new 210000292 rev C board with..
    1. New 2MB ASYNC SRAM Chip
    2. New Leak Sensor
    3. New 80Hzs Aout
    4. New PCB Rev Circuit
    5. New Thermal Controller Circuit
    6. New Ferrites
    7. Updated Voltage monitor circuits

Ver 41
1. Fixed board version address to 0x500401.
2. Fixed heater output to make it tristate untill TRIBUF is written low.
3. made filter external Register a read write register.
4. Fixed thermal Muxed ADC serial interface bug.  read bit count needed to be changed to <24
5. Redesigned write registers to be clock driven and strobe enabled.  keep consistant with 2489 and FLR
6. Fixed bug in AOUT machine. data bit 10 & 8 were devined as PRFRLDATA rather then DATA to input of module.

Ver 42
1. Added 500002 dsp reset strobe. Forgot to add it in new mem map design.

Ver 43
1. Inverted Lampon signal so it matches 250 board low active. 
2. Set up TRIREG with a double invert one before and after register. this will allow proper state in stage 
   two of proper active state.

Ver 44
1. fixed PWM drive generated latch by sync proper signals.  Not function is the same as 2489. 
   no software change nessisary.

Ver 45
1. modified Analog out register definition via Adils request.  MemMap rev D required.

Ver 46
1. Adil requested for the Aout registers to be changed again. MemMap rev E required.
Ver 46B
1. Fixed ver id read register address location to 1A.

Ver 47
1. This is our first attempt of FIFO.  Image given to Fred Carter. Image needs new DSP build to function.

Ver 48
1. Same as ver 46B with new FPGA ver.  Adil wanted a new ver number instead of 46B.

Ver 49
1. Fixed ver id read register address location to 1A.
2. Added CE_n to sensitivity list on procces in DSP read from FPGA machine.
3. reduced ce time on fpga to ca adc state machine by 2 states.

Ver 4A
1. Fixed CA ADC Read Machine bug for DSP development


Ver 4B
1. Fixed CA ADC Read Machine bug for DSP development (syncronized BUSY signal)

ver 4C
1. FIRST FPGA BUILD ON NEW TOOLS!!!!
2. changed write strobe back to 18MHz.  the strobe has been at 9MHz for some time and
   9MHz was not the correct strobe machine clock freq.
3. Enabled the SDRAM Memory.

ver 4D
1. fixed a DSP bug for Fred.  Moved the last 2 bits of 18 bit read to top of 3rd register.
   old ver =>  A1=0 A0=0   then   A1=1 A0=0   Then   A1=0 A0=1
   new ver =>  A1=0 A0=0   then   A1=1 A0=0   Then   A1=1 A0=1

Ver 5B
1. Enables GPU Memory.
   CS4 & CS8 
    set CS4BAR register 0xfffA5c to 0x4007   
    set CS8BAR register 0xfffA6c to 0x4007 
    (Bits 2,1,0 changed to '111'  for 1MB address space) 
   CS4 
    set CS4OR register 0xfffA5E to 0x5930   
    (Bits 14,13: changed to '10' for Upper Byte) 
    (Bits 9,8,7,6: number of Wait States (4)) 
   CS8 
    set CS8OR register 0xfffA6E to 0x3930   
    (Bits 14,13: changed to '01' for Lower Byte)     
    (Bits 9,8,7,6: number of Wait States (4)) 

Ver 5C
1.  Added seperate enable to shut down thermal control ADC (register 500019 bit 2).
2.  Added CS8 to AND gate input for tranciever enable.



........ REWORKS REQUIRED FOR THIS IMAGE ..........
new 210000292 RevC board




.........SOFTWARE INSTRUCTIONS...........................
1. Be careful not to load into a 250 board.  Use brd ID to determine what version to load.
2. Do not load into 210000292 Rev B boards.  






.........QUARTUS INSTRUCTIONS...........................
Ensure the following special pin assignments are made other then just pin number
	# Analysis & Synthesis Assignments
	# ================================
	set_instance_assignment -name POWER_UP_LEVEL HIGH -to B_DATA_CS_n
	set_instance_assignment -name POWER_UP_LEVEL HIGH -to BBCS9_n
	set_instance_assignment -name POWER_UP_LEVEL HIGH -to BCS9_n
	set_instance_assignment -name POWER_UP_LEVEL LOW -to DSP_SOFTWARE_RST_n
	set_instance_assignment -name POWER_UP_LEVEL LOW -to FLTR_WHL_EN
	set_instance_assignment -name POWER_UP_LEVEL HIGH -to FLTR_WHL_RST
	set_instance_assignment -name POWER_UP_LEVEL HIGH -to FLTR_WHL_HOLD
	set_instance_assignment -name POWER_UP_LEVEL LOW -to FLTR_STRB
	set_instance_assignment -name POWER_UP_LEVEL LOW -to HEATER_PWM
	set_instance_assignment -name POWER_UP_LEVEL HIGH -to FAN_PWM
	set_instance_assignment -name POWER_UP_LEVEL LOW -to LAMP_ON
	set_instance_assignment -name POWER_UP_LEVEL HIGH -to IRQ5_n
	set_instance_assignment -name POWER_UP_LEVEL HIGH -to MEM_CS_n
	set_instance_assignment -name POWER_UP_LEVEL HIGH -to REFCS_n
	set_instance_assignment -name POWER_UP_LEVEL LOW -to LED_LOOP_STRB
	set_instance_assignment -name POWER_UP_LEVEL HIGH -to TRI_REG