--
-- VHDL Architecture PLD_2998_lib.BUF8.RTL
--
-- Created:
--          Justin Deary
--           8 bit buffer
--
-- using Mentor Graphics HDL Designer(TM) 2004.1a (Build 15)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY BUF_8_out IS
     PORT( 
        din : IN 	   STD_LOGIC_VECTOR (7 downto 0); 
        do0 : OUT    std_logic;
        do1 : OUT    std_logic;
        do2 : OUT    std_logic;
        do3 : OUT    std_logic;
        do4 : OUT    std_logic;
        do5 : OUT    std_logic;
        do6 : OUT    std_logic;
        do7 : OUT    std_logic
     );
  
END ENTITY BUF_8_out;

--
ARCHITECTURE RTL OF BUF_8_out IS
BEGIN
 
 do0 <= din(0);
 do1 <= din(1);  
 do2 <= din(2);  
 do3 <= din(3);  
 do4 <= din(4);
 do5 <= din(5);  
 do6 <= din(6);  
 do7 <= din(7);   
  
END ARCHITECTURE RTL;