--
-- VHDL Architecture PLD_2998_lib.CLOCK_500HZ.RTL
--
-- Created:
--          by - dearyj.UNKNOWN (DEARY-JUSTIN)
--          at - 07:35:05 07/30/2004
--
-- using Mentor Graphics HDL Designer(TM) 2004.1 (Build 41)
-- DSP 500 HZ THREAD CLOCK GENERATOR
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY CLOCK_500HZ IS
port(	RESET           :	  in std_logic;
      CLK36MHZ    :   in std_logic;

	    CLK500HZ        :	  buffer std_logic
);   
END ENTITY CLOCK_500HZ;

--

ARCHITECTURE RTL OF CLOCK_500HZ IS

BEGIN


		     
    process (RESET,CLK36MHZ)
    		VARIABLE i : integer range 0 TO 36000;   
      begin
	      
      if (RESET = '1')then
          CLK500HZ <= '0';
          i := 0;
          
      elsif rising_edge(CLK36MHZ) then
          if(i < 36000) then
              i := i + 1;
          else 
             CLK500HZ <= not CLK500HZ;
              i := 0;
	      end if;
      end if;    
    end process;
    
END ARCHITECTURE RTL;