--
-- VHDL Architecture PLD_2998_lib.DATA_FIFO.RTL
--
-- Created:
--          by - DearyJ.UNKNOWN (DEARY-JUSTIN)
--          at - 09:10:19 11/14/2005
--
-- using Mentor Graphics HDL Designer(TM) 2004.1a (Build 15)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY ADC_read_machn_DSP_cntrl IS
  port(	DATAIN:	     in std_logic_vector(23 downto 0); 
        CE_n:        in  std_logic;   
        STRB_n:      in  std_logic;
        SHIFT_DATA:  in  std_logic;
	      DATAOUT:	    out std_logic_vector(7 downto 0)
  );
  
END ENTITY ADC_read_machn_DSP_cntrl;

--
ARCHITECTURE RTL OF ADC_read_machn_DSP_cntrl IS
  
SIGNAL CURRENT_STATE   :INTEGER  RANGE 0 to 4; -- MACHINE CURRENT STATE DEFINITION
SIGNAL NEXT_STATE      :INTEGER  RANGE 0 to 4; -- MACHINE NEXT STATE DEFINITION
SIGNAL Do              :std_logic_vector(7 downto 0);
BEGIN


DATAOUT <= Do when (CE_n = '0') else       --case statment tristates bus when CS is unactive.
(others => 'Z');


-- THIS PROCESS HOLDS THE SEQUENTIAL "CURRENT STATE" GENERATOR FOR THE STATE MACHINE.  
  SEQ: PROCESS(STRB_n,SHIFT_DATA,CE_n)                                
  begin
  if SHIFT_DATA = '1' then    
     CURRENT_STATE <= 0;    
  elsif CE_n = '0' then 
     if falling_edge(STRB_n) then             -- every reset brings machine to initial state
        CURRENT_STATE <=  NEXT_STATE;         -- state change on rising  edge of clock          
     end if;
  end if;
  END PROCESS SEQ; 
   

-- THIS PROCESS HOLDS THE NEXT STATE COMBINATORIAL LOGIC FOR THE STATE MACHINE.  
  COMB: PROCESS(CURRENT_STATE)     
  begin 
   Case (CURRENT_STATE) is
         
     when 0  =>              -- wait for first strobe falling edge 
        Do <= (X"FF");
        NEXT_STATE <= 1;
        
     when 1  =>               
        Do <= DATAIN(23 downto 16);
        NEXT_STATE <= 2;
          
     when 2  =>               
        Do <= DATAIN(15 downto 8);
        NEXT_STATE <= 3;
         
     when 3  =>               
        Do <= DATAIN(7 downto 0);
        NEXT_STATE <= 4;
        
     when 4  =>               -- If DSP reads to many 8 bit values (>3) it will read FF! 
        Do <= (X"FF");
        NEXT_STATE <= 4; 
                                    
     when others  =>  
        Do <= (X"FF");  
             
end Case;       
END PROCESS COMB;  


END ARCHITECTURE RTL;




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