--
-- VHDL Architecture PLD_2998_lib.DECODE.RTL
--
-- Created:
--          by - dearyj.UNKNOWN (DEARY-JUSTIN)
--          at - 21:59:16 07/21/2004
--
-- using Mentor Graphics HDL Designer(TM) 2004.1 (Build 41)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;




entity DECODER is
port(	I:	in std_logic_vector(2 downto 0);
      EN1: in std_logic;
      EN2: in std_logic;
      EN0: in std_logic;      
	    Y:	out std_logic_vector(7 downto 0)
);
end DECODER;

-------------------------------------------------

architecture RTL of DECODER is
begin

    -- process statement

    process (I,EN1,EN2,EN0)
    begin
    
        -- use case statement 
    if (EN1 = '0' or EN2 = '0' or EN0 = '0')then
        Y <= "00000000";
    else 
      case I is
	    when "000" => Y <= "00000001";
	    when "001" => Y <= "00000010";
	    when "010" => Y <= "00000100";
	    when "011" => Y <= "00001000";
	    when "100" => Y <= "00010000";
	    when "101" => Y <= "00100000";
	    when "110" => Y <= "01000000";
	    when "111" => Y <= "10000000";
    	      	      
	    when others => Y <= "00000000";
	    end case;
	  
	  end if;

    end process;
	
end RTL;