--
-- VHDL Architecture PLD_2998_lib.DSPRESET.RTL
--
-- Created:
--          by - DearyJ.UNKNOWN (DEARY-JUSTIN)
--          at - 08:12:34 10/07/2004
--
-- using Mentor Graphics HDL Designer(TM) 2004.1a (Build 15)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY DSPRESET IS
  PORT(  
      --INPUTS FROM BOARD AND CPU2000
    CLOCK          : IN  STD_LOGIC;                     -- pos_edge    - CLK 9MHZ/8      
    DSP_RST_STRB   : IN  STD_LOGIC;            
          
    --OUTPUTS TO PERSONALITY BOARD DSP RESET LINE
    DSPRST        : OUT  STD_LOGIC);                                

END ENTITY DSPRESET;


--******************************************************************** 
--THE ARCHITECTURE BODY DESCRIBES THE FUNCTIONAL COMPOSITION OF THIS DESIGN
ARCHITECTURE RTL OF DSPRESET IS
    SIGNAL CURRENT_STATE       : INTEGER  RANGE 0 to 3; --  MACHINE CURRENT STATE DEFINITION
    SIGNAL NEXT_STATE          : INTEGER  RANGE 0 to 3; --  MACHINE NEXT STATE DEFINITION
BEGIN



-- #############################################################################################################
-- DSP RESET State Machine writes a 220ns reset pulse to the DSP while the 3.3v host port data bus
-- is completely tristated.  This allows for the host port data bus mode setting resisters to set the proper
-- DSP mode with nothing else driving the bus.  
--############################# BEGIN DSPRESET_SEQ PROCESS #######################################################
 -- THIS PROCESS HOLDS THE SEQUENTIAL "CURRENT STATE" GENERATOR FOR THE DSPRESET STATE MACHINE. 

  DSPRESET_SEQ: PROCESS(CLOCK,NEXT_STATE,DSP_RST_STRB)                                
      begin                  
          if (DSP_RST_STRB = '1')  then
            CURRENT_STATE <=  0;                                        
          elsif rising_edge(CLOCK) then
              CURRENT_STATE <=  NEXT_STATE;    -- state change on rising  edge of clock
          end if;  
    END PROCESS DSPRESET_SEQ;
             
  
--############################# BEGIN DSPRESET_COMB PROCESS #######################################################
-- THIS PROCESS HOLDS THE COMBINATORIAL LOGIC FOR THE DSPRESET STATE MACHINE. 

  DSPRESET_COMB: PROCESS(CURRENT_STATE)   
    
  begin 
                 
      Case (CURRENT_STATE) is

      when 0     =>     NEXT_STATE   <=  1; 
                        DSPRST       <= '0';
         
      when 1     =>     NEXT_STATE   <=  2; 
                        DSPRST       <= '0';
         
      when 2     =>     NEXT_STATE   <=  3; 
                        DSPRST       <= '0';
                                 
      when 3     =>     NEXT_STATE   <=  3; 
                        DSPRST       <= '1'; 


      when others =>    NEXT_STATE   <=  3; 
                        DSPRST       <= '1';           
   End Case;

END PROCESS DSPRESET_COMB;
            

END ARCHITECTURE RTL;