-- -- VHDL Architecture THERMAL_CNTRL_lib.MEM_MAP_REG.rtl -- -- Created: -- Justin Deary 9/1/2006 -- Memory map decode for FLR FPGA -- -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY MEM_MAP_REG IS PORT( RESET : IN STD_LOGIC; -- high active - PLD Reset CLOCK : IN STD_LOGIC; PRFRLAD : IN STD_LOGIC_VECTOR (5 downto 0); ADD10 : IN STD_LOGIC; W_STRB : IN STD_LOGIC; R_STRB : IN STD_LOGIC; DATA : INOUT STD_LOGIC_VECTOR (7 downto 0); BCS5_n : OUT STD_LOGIC; -- disables CS to level shifter durring a strobe read -- prevents bus contension from board read registers -- CPU2000 READS/Writes/Strobes -- CS OFFSET 5 --REG_00001 : OUT STD_LOGIC_VECTOR (7 downto 0); -- reserved (old led strobe) STRB_W_00002 : OUT STD_LOGIC; --REG_00003 : OUT STD_LOGIC_VECTOR (7 downto 0); -- reserved STRB_W_00004 : OUT STD_LOGIC; -- sftware loops write strobe W_REG_00005 : OUT STD_LOGIC_VECTOR (7 downto 0); -- status/power leds and event outputs W_REG_00006 : OUT STD_LOGIC_VECTOR (7 downto 0); -- filter wheel motor enable/hold W_REG_00007 : OUT STD_LOGIC_VECTOR (7 downto 0); -- lamp control R_REG_00008 : IN STD_LOGIC_VECTOR (7 downto 0); -- leak detect, fuse detect, and lamp status R_REG_00009 : IN STD_LOGIC_VECTOR (7 downto 0); -- FPGA Version --REG_0000A : OUT STD_LOGIC_VECTOR (7 downto 0); -- not used --REG_0000B : OUT STD_LOGIC_VECTOR (7 downto 0); -- not used --REG_0000C : OUT STD_LOGIC_VECTOR (7 downto 0); -- not used --REG_0000D : OUT STD_LOGIC_VECTOR (7 downto 0); -- not used --REG_0000E : OUT STD_LOGIC_VECTOR (7 downto 0); -- not used --REG_0000F : OUT STD_LOGIC_VECTOR (7 downto 0); -- not used W_REG_00010 : OUT STD_LOGIC_VECTOR (7 downto 0); -- event input to DSP level select W_REG_00011 : OUT STD_LOGIC_VECTOR (7 downto 0); -- event input to DSP enable select W_REG_00012 : OUT STD_LOGIC_VECTOR (7 downto 0); -- qspi enable --REG_00013 : OUT ARCHITECTURE rtl OF MEM_MAP_REG ISSTD_LOGIC_VECTOR (7 downto 0); -- not used --REG_00014 : OUT STD_LOGIC_VECTOR (7 downto 0); -- not used W_REG_00015 : OUT STD_LOGIC_VECTOR (7 downto 0); -- debug register --REG_00016 : OUT STD_LOGIC_VECTOR (7 downto 0); -- not used --REG_00017 : OUT STD_LOGIC_VECTOR (7 downto 0); -- not used --REG_00018 : OUT STD_LOGIC_VECTOR (7 downto 0); -- not used W_REG_00019 : OUT STD_LOGIC_VECTOR (7 downto 0); -- tristate exernal registers STRB_W_0001A : OUT STD_LOGIC; -- AOUT filters STRB_W_0001B : OUT STD_LOGIC; -- AOUT Start Control Register W_REG_0001C : OUT STD_LOGIC_VECTOR (7 downto 0); -- reserved for AOUT CH1 for a 32 bit read W_REG_0001D : OUT STD_LOGIC_VECTOR (7 downto 0); -- AOUT CH1 read data 23 downto 16 W_REG_0001E : OUT STD_LOGIC_VECTOR (7 downto 0); -- AOUT CH1 read data 15 downto 8 W_REG_0001F : OUT STD_LOGIC_VECTOR (7 downto 0); -- AOUT CH1 read data 7 downto 0 W_REG_00020 : OUT STD_LOGIC_VECTOR (7 downto 0); -- reserved for AOUT CH2 for a 32 bit read W_REG_00021 : OUT STD_LOGIC_VECTOR (7 downto 0); -- AOUT CH2 read data 23 downto 16 W_REG_00022 : OUT STD_LOGIC_VECTOR (7 downto 0); -- AOUT CH2 read data 15 downto 8 W_REG_00023 : OUT STD_LOGIC_VECTOR (7 downto 0); -- AOUT CH2 read data 7 downto 0 W_REG_00024 : OUT STD_LOGIC_VECTOR (7 downto 0); -- AOUT CH1 instruction register W_REG_00025 : OUT STD_LOGIC_VECTOR (7 downto 0); -- AOUT CH2 instruction register --REG_00026 : OUT STD_LOGIC_VECTOR (7 downto 0); -- not used --REG_00027 : OUT STD_LOGIC_VECTOR (7 downto 0); -- not used --REG_00028 : OUT STD_LOGIC_VECTOR (7 downto 0); -- not used --REG_00029 : OUT STD_LOGIC_VECTOR (7 downto 0); -- not used R_REG_0002A : IN STD_LOGIC_VECTOR (7 downto 0); -- Thermal ADC Ch0 bits (23 downto 16) R_REG_0002B : IN STD_LOGIC_VECTOR (7 downto 0); -- Thermal ADC Ch0 bits (15 downto 8) R_REG_0002C : IN STD_LOGIC_VECTOR (7 downto 0); -- Thermal ADC Ch0 bits (7 downto 0) --REG_0002D : OUT STD_LOGIC_VECTOR (7 downto 0); -- not used R_REG_0002E : IN STD_LOGIC_VECTOR (7 downto 0); -- Thermal ADC Ch1 bits (23 downto 16) R_REG_0002F : IN STD_LOGIC_VECTOR (7 downto 0); -- Thermal ADC Ch1 bits (15 downto 8) R_REG_00030 : IN STD_LOGIC_VECTOR (7 downto 0); -- Thermal ADC Ch1 bits (7 downto 0) --REG_00031 : OUT STD_LOGIC_VECTOR (7 downto 0); -- not used --REG_00032 : IN STD_LOGIC_VECTOR (7 downto 0); -- not used --REG_00033 : IN STD_LOGIC_VECTOR (7 downto 0); -- not used --REG_00034 : IN STD_LOGIC_VECTOR (7 downto 0); -- not used --REG_00035 : OUT STD_LOGIC_VECTOR (7 downto 0); -- not used --W_REG_00036 : OUT STD_LOGIC_VECTOR (7 downto 0); -- not used --W_REG_00037 : OUT STD_LOGIC_VECTOR (7 downto 0); -- not used --W_REG_00038 : OUT STD_LOGIC_VECTOR (7 downto 0); -- not used --W_REG_00039 : OUT STD_LOGIC_VECTOR (7 downto 0); -- not used W_REG_0003A : OUT STD_LOGIC_VECTOR (7 downto 0); -- thermal controller pwm2 freq counter (15 downto 8) W_REG_0003B : OUT STD_LOGIC_VECTOR (7 downto 0); -- thermal controller pwm2 freq counter (7 downto 0) W_REG_0003C : OUT STD_LOGIC_VECTOR (7 downto 0); -- thermal controller pwm2 duty cycle counter (15 downto 8) W_REG_0003D : OUT STD_LOGIC_VECTOR (7 downto 0) -- thermal controller pwm2 duty cycle counter (7 downto 0) --REG_0003E : OUT STD_LOGIC_VECTOR (7 downto 0); -- not used --REG_0003F : OUT STD_LOGIC_VECTOR (7 downto 0); -- not used ); END ENTITY MEM_MAP_REG; ARCHITECTURE rtl OF MEM_MAP_REG IS SIGNAL ADR : STD_LOGIC_VECTOR (11 downto 0); SIGNAL RW_REG_0001A : STD_LOGIC_VECTOR (7 downto 0); -- for read write register BEGIN ADR <= ('0' & ADD10 & "0000" & PRFRLAD); -- THIS PROCESS HOLDS THE READ REGISTER DEFINITIONS READREG : PROCESS(R_STRB,RESET) begin --STRB_R_0000X <='1'; -- ensure all strobes are unactive upon entering process BCS5_n <= '0'; DATA <= "ZZZZZZZZ"; -- Keeps bus tristated unless read address is legal if (R_STRB = '1') then -- reads to bus on falling edge of strobe case (ADR) is when x"401" => BCS5_n <= '1'; -- board Rev --BCS5_n needs to be high for any R strb when x"008" => DATA <= R_REG_00008; BCS5_n <= '0'; when x"009" => DATA <= R_REG_00009; BCS5_n <= '0'; when x"01A" => DATA <= RW_REG_0001A; BCS5_n <= '0'; when x"02A" => DATA <= R_REG_0002A; BCS5_n <= '0'; when x"02B" => DATA <= R_REG_0002B; BCS5_n <= '0'; when x"02C" => DATA <= R_REG_0002C; BCS5_n <= '0'; when x"02E" => DATA <= R_REG_0002E; BCS5_n <= '0'; when x"02F" => DATA <= R_REG_0002F; BCS5_n <= '0'; when x"030" => DATA <= R_REG_00030; BCS5_n <= '0'; when others => DATA <= "ZZZZZZZZ"; end case; end if; END PROCESS READREG; -- THIS PROCESS HOLDS THE WRITE REGISTER DEFINITIONS WRITEREG : PROCESS(RESET,W_STRB,CLOCK) begin -- ensure all strobes are unactive upon entering process STRB_W_00002 <='0'; STRB_W_00004 <='0'; STRB_W_0001A <='0'; STRB_W_0001B <='0'; if rising_edge(CLOCK) then if (RESET = '1') then --resets write reg (SET TO RESET UNACTIVE LOGIC STATE!) W_REG_00005 <= x"00"; W_REG_00006 <= x"00"; W_REG_00007 <= x"00"; W_REG_00010 <= x"00"; W_REG_00011 <= x"00"; W_REG_00012 <= x"00"; W_REG_00015 <= x"00"; W_REG_00019 <= x"00"; RW_REG_0001A <= x"00"; W_REG_0001C <= x"00"; W_REG_0001D <= x"00"; W_REG_0001E <= x"00"; W_REG_0001F <= x"00"; W_REG_00020 <= x"00"; W_REG_00021 <= x"00"; W_REG_00022 <= x"00"; W_REG_00023 <= x"00"; W_REG_00024 <= x"00"; W_REG_00025 <= x"00"; W_REG_0003A <= x"80"; W_REG_0003B <= x"00"; W_REG_0003C <= x"40"; W_REG_0003D <= x"00"; elsif (W_STRB = '1') then -- writes to register on rissing edge of strobe case (ADR) is when x"002" => STRB_W_00002 <= '1'; when x"004" => STRB_W_00004 <= '1'; when x"005" => W_REG_00005 <= DATA; when x"006" => W_REG_00006 <= DATA; when x"007" => W_REG_00007 <= DATA; when x"010" => W_REG_00010 <= DATA; when x"011" => W_REG_00011 <= DATA; when x"012" => W_REG_00012 <= DATA; when x"015" => W_REG_00015 <= DATA; when x"019" => W_REG_00019 <= not(DATA); when x"01A" => STRB_W_0001A <= '1'; RW_REG_0001A <= DATA; when x"01B" => STRB_W_0001B <= '1'; when x"01C" => W_REG_0001C <= DATA; when x"01D" => W_REG_0001D <= DATA; when x"01E" => W_REG_0001E <= DATA; when x"01F" => W_REG_0001F <= DATA; when x"020" => W_REG_00020 <= DATA; when x"021" => W_REG_00021 <= DATA; when x"022" => W_REG_00022 <= DATA; when x"023" => W_REG_00023 <= DATA; when x"024" => W_REG_00024 <= DATA; when x"025" => W_REG_00025 <= DATA; when x"03A" => W_REG_0003A <= DATA; when x"03B" => W_REG_0003B <= DATA; when x"03C" => W_REG_0003C <= DATA; when x"03D" => W_REG_0003D <= DATA; when others => null; end case; end if; end if; END PROCESS WRITEREG; END ARCHITECTURE rtl;