-- -- Created: -- by - DEARY-JUSTIN -- 09/19/2006 -- -- VHDL CODE WRITES 32 BITS TO DAC1220 WITH A SPI -- THIS MACHINE REPLACES THE OLD TONY S. MACHINE. -- LIMITATIONS ARE NO DAC RESET OR READS AVAILIBLE -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY NEWDAC1220 IS PORT( CLOCK : IN std_logic; PAR_DATA : IN std_logic_vector (31 DOWNTO 0); RESET : IN std_logic; START_BIT : IN std_logic; START_STRB : IN std_logic; CS : OUT std_logic; SCLK : OUT std_logic; SDO : OUT std_logic ); END ENTITY NEWDAC1220; -- ARCHITECTURE RTL OF NEWDAC1220 IS SIGNAL CURRENT_STATE :INTEGER RANGE 0 to 70; -- MACHINE CURRENT STATE DEFINITION SIGNAL NEXT_STATE :INTEGER RANGE 0 to 70; -- MACHINE NEXT STATE DEFINITION BEGIN -- THIS PROCESS HOLDS THE SEQUENTIAL "CURRENT STATE" GENERATOR FOR THE SPI STATE MACHINE. SPI_SEQ: PROCESS(CLOCK,RESET,START_STRB) begin if RESET = '1' then CURRENT_STATE <= 0; elsif (START_STRB = '1') and (START_BIT = '1') then CURRENT_STATE <= 1; elsif rising_edge(CLOCK) then -- every reset brings machine to initial state CURRENT_STATE <= NEXT_STATE; -- state change on rising edge of clock end if; END PROCESS SPI_SEQ; -- THIS PROCESS HOLDS THE NEXT STATE COMBINATORIAL LOGIC FOR THE SPI STATE MACHINE. SPI_COMB: PROCESS(CURRENT_STATE) begin Case (CURRENT_STATE) is when 0 => -- wait untill start strobe CS <= '1'; SCLK <= '0'; SDO <= '0'; NEXT_STATE <= 0; when 1 => -- wait t10 (see dac1220 spec) CS <= '0'; SCLK <= '0'; SDO <= '0'; NEXT_STATE <= 2; when 2 => -- wait t10 (see dac1220 spec) CS <= '0'; SCLK <= '0'; SDO <= '0'; NEXT_STATE <= 3; when 3 => -- start sending inst register CS <= '0'; SCLK <= '1'; SDO <= PAR_DATA(31); NEXT_STATE <= 4; when 4 => CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(31); NEXT_STATE <= 5; when 5 => CS <= '0'; SCLK <= '1'; SDO <= PAR_DATA(30); NEXT_STATE <= 6; when 6 => CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(30); NEXT_STATE <= 7; when 7 => CS <= '0'; SCLK <= '1'; SDO <= PAR_DATA(29); NEXT_STATE <= 8; when 8 => CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(29); NEXT_STATE <= 9; when 9 => CS <= '0'; SCLK <= '1'; SDO <= PAR_DATA(28); NEXT_STATE <= 10; when 10 => CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(28); NEXT_STATE <= 11; when 11 => CS <= '0'; SCLK <= '1'; SDO <= PAR_DATA(27); NEXT_STATE <= 12; when 12 => CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(27); NEXT_STATE <= 13; when 13 => CS <= '0'; SCLK <= '1'; SDO <= PAR_DATA(26); NEXT_STATE <= 14; when 14 => CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(26); NEXT_STATE <= 15; when 15 => CS <= '0'; SCLK <= '1'; SDO <= PAR_DATA(25); NEXT_STATE <= 16; when 16 => CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(25); NEXT_STATE <= 17; when 17 => CS <= '0'; SCLK <= '1'; SDO <= PAR_DATA(24); NEXT_STATE <= 18; when 18 => -- end of sending inst register CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(24); NEXT_STATE <= 19; when 19 => -- wait t9 (see dac1220 spec) CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(24); NEXT_STATE <= 20; when 20 => -- wait t9 (see dac1220 spec) CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(24); NEXT_STATE <= 21; when 21 => -- start sending byte 1 CS <= '0'; SCLK <= '1'; SDO <= PAR_DATA(23); NEXT_STATE <= 22; when 22 => CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(23); NEXT_STATE <= 23; when 23 => CS <= '0'; SCLK <= '1'; SDO <= PAR_DATA(22); NEXT_STATE <= 24; when 24 => CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(22); NEXT_STATE <= 25; when 25 => CS <= '0'; SCLK <= '1'; SDO <= PAR_DATA(21); NEXT_STATE <= 26; when 26 => CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(21); NEXT_STATE <= 27; when 27 => CS <= '0'; SCLK <= '1'; SDO <= PAR_DATA(20); NEXT_STATE <= 28; when 28 => CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(20); NEXT_STATE <= 29; when 29 => CS <= '0'; SCLK <= '1'; SDO <= PAR_DATA(19); NEXT_STATE <= 30; when 30 => CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(19); NEXT_STATE <= 31; when 31 => CS <= '0'; SCLK <= '1'; SDO <= PAR_DATA(18); NEXT_STATE <= 32; when 32 => CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(18); NEXT_STATE <= 33; when 33 => CS <= '0'; SCLK <= '1'; SDO <= PAR_DATA(17); NEXT_STATE <= 34; when 34 => CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(17); NEXT_STATE <= 35; when 35 => CS <= '0'; SCLK <= '1'; SDO <= PAR_DATA(16); NEXT_STATE <= 36; when 36 => -- end sending byte 1 CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(16); NEXT_STATE <= 37; when 37 => -- Start sending byte 2 CS <= '0'; SCLK <= '1'; SDO <= PAR_DATA(15); NEXT_STATE <= 38; when 38 => CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(15); NEXT_STATE <= 39; when 39 => CS <= '0'; SCLK <= '1'; SDO <= PAR_DATA(14); NEXT_STATE <= 40; when 40 => CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(14); NEXT_STATE <= 41; when 41 => CS <= '0'; SCLK <= '1'; SDO <= PAR_DATA(13); NEXT_STATE <= 42; when 42 => CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(13); NEXT_STATE <= 43; when 43 => CS <= '0'; SCLK <= '1'; SDO <= PAR_DATA(12); NEXT_STATE <= 44; when 44 => CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(12); NEXT_STATE <= 45; when 45 => CS <= '0'; SCLK <= '1'; SDO <= PAR_DATA(11); NEXT_STATE <= 46; when 46 => CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(11); NEXT_STATE <= 47; when 47 => CS <= '0'; SCLK <= '1'; SDO <= PAR_DATA(10); NEXT_STATE <= 48; when 48 => CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(10); NEXT_STATE <= 49; when 49 => CS <= '0'; SCLK <= '1'; SDO <= PAR_DATA(9); NEXT_STATE <= 50; when 50 => CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(9); NEXT_STATE <= 51; when 51 => CS <= '0'; SCLK <= '1'; SDO <= PAR_DATA(8); NEXT_STATE <= 52; when 52 => -- end sending byte 2 CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(8); NEXT_STATE <= 53; when 53 => -- if instruction reg defined as 3 bytes if PAR_DATA(30) = '0' then -- then start sending byte 3 CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(8); NEXT_STATE <= 69; else CS <= '0'; SCLK <= '1'; SDO <= PAR_DATA(7); NEXT_STATE <= 54; end if; when 54 => CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(7); NEXT_STATE <= 55; when 55 => CS <= '0'; SCLK <= '1'; SDO <= PAR_DATA(6); NEXT_STATE <= 56; when 56 => CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(6); NEXT_STATE <= 57; when 57 => CS <= '0'; SCLK <= '1'; SDO <= PAR_DATA(5); NEXT_STATE <= 58; when 58 => CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(5); NEXT_STATE <= 59; when 59 => CS <= '0'; SCLK <= '1'; SDO <= PAR_DATA(4); NEXT_STATE <= 60; when 60 => CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(4); NEXT_STATE <= 61; when 61 => CS <= '0'; SCLK <= '1'; SDO <= PAR_DATA(3); NEXT_STATE <= 62; when 62 => CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(3); NEXT_STATE <= 63; when 63 => CS <= '0'; SCLK <= '1'; SDO <= PAR_DATA(2); NEXT_STATE <= 64; when 64 => CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(2); NEXT_STATE <= 65; when 65 => CS <= '0'; SCLK <= '1'; SDO <= PAR_DATA(1); NEXT_STATE <= 66; when 66 => CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(1); NEXT_STATE <= 67; when 67 => CS <= '0'; SCLK <= '1'; SDO <= PAR_DATA(0); NEXT_STATE <= 68; when 68 => CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(0); NEXT_STATE <= 69; when 69 => CS <= '0'; SCLK <= '0'; SDO <= PAR_DATA(0); NEXT_STATE <= 70; when 70 => CS <= '1'; SCLK <= '0'; SDO <= PAR_DATA(0); NEXT_STATE <= 0; when others => CS <= '1'; SCLK <= '0'; SDO <= '0'; NEXT_STATE <= 0; end Case; END PROCESS SPI_COMB; END ARCHITECTURE RTL;