--
-- Created:
--          Justin Deary
--          08/31/2006
--          QSPI CHIP SELECT DECODE AND SIGNAL BUFFERS
-- 
--


LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY QSPI_CNTRL IS
  PORT(  
  PCSO_n     : in std_logic;    -- cs from CPU2000
  PCS1_n     : in std_logic;    -- cs from CPU2000 
  PCS2_n     : in std_logic;    -- cs from CPU2000  
  PCS3_n     : in std_logic;    -- cs from CPU2000  
  QSPI_DOUT  : in std_logic;    -- data from CPU2000
  QSPI_CLK   : in std_logic;    -- sclk from CPU2000  
  QSPI_DIN   : out std_logic;   -- data to CPU2000
  
    
  PCS0          : out std_logic;  -- cs to analog brd
  PCS1          : out std_logic;  -- cs to analog brd
  CS_MPLX_AD_n  : out std_logic;  -- cs to sys ADC
  QSPI_DATA_IN  : in std_logic;   -- data in from devices
  QSPI_DATA_OUT : out std_logic;  -- data to devices
  SCK           : out std_logic);  -- sclk to devices
 END ENTITY QSPI_CNTRL;


--
ARCHITECTURE RTL OF QSPI_CNTRL IS

SIGNAL PCS     : STD_LOGIC_VECTOR (3 downto 0);
BEGIN
    PCS <= (PCS3_n & PCS2_n & PCS1_n & PCSO_n);  
    QSPI_DATA_OUT <= QSPI_DOUT;
    SCK <= QSPI_CLK;
    QSPI_DIN <= QSPI_DATA_IN;
    
    process (PCS)
    begin
    PCS0 <= '1';
    PCS1 <= '1';
    CS_MPLX_AD_n <= '1';        
        -- Decode QSPI CS for peripheral devices 
      case PCS is
	    when "0011" => CS_MPLX_AD_n <= '0';	         
	    when "0100" => PCS0 <= '0';
                     PCS1 <= '0';
	    when "0101" => PCS1 <= '0'; 
	    when "0110" => PCS0 <= '0';    	      	      
	    when others =>     PCS0 <= '1';
                         PCS1 <= '1';
                         CS_MPLX_AD_n <= '1'; 
	    end case;
	  
    end process;  
  
END ARCHITECTURE RTL;