--
-- VHDL Architecture SPI_CNTRL.rtl
--
--
-- Created:
--          by - JUSTIN DEARY
--          at - 06/14/2006
--
-- Mentor Graphics HDL Designer(TM) 2004.1a (Build 15)


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY SPI_CNTRL_tester IS
   PORT( 
      CS_n         : IN     STD_LOGIC;
      DATA2AD      : IN     STD_LOGIC;
      DATA_CH0     : IN     STD_LOGIC_VECTOR (23 DOWNTO 0);
      DATA_CH1     : IN     STD_LOGIC_VECTOR (23 DOWNTO 0);
      DATA_CH3     : IN     STD_LOGIC_VECTOR (23 DOWNTO 0);
      SCLK         : IN     STD_LOGIC;
      CLOCK        : OUT    STD_LOGIC;
      DATA_FROM_AD : OUT    STD_LOGIC;
      DATA_RDY     : OUT    STD_LOGIC;
      RESET        : OUT    STD_LOGIC;
      FASTCLOCK    : OUT    STD_LOGIC
   );

-- Declarations

END SPI_CNTRL_tester ;
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--AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
ARCHITECTURE RTL OF SPI_CNTRL_TESTER IS

SIGNAL    sysclock	    :	std_logic := '1';
SIGNAL    sysclock2	    :	std_logic := '1';
SIGNAL    ready	       :	std_logic := '0';
CONSTANT  DATA_test    : STD_LOGIC_VECTOR :=  B"0101_1010_1000_0100_0010_0001";



BEGIN
  
  
  -- GENERATE SYSTEM RESET
  RESET <= '0', '1' after 5 ns, '0' after 50000 ns;
  
  --GENERATE CLOCK SIGNAL FOR TEST											     
  sysclock <= not sysclock after 4500 ns;         
  CLOCK <= sysclock;
  
  sysclock2 <= not sysclock2 after 50 ns;          
  FASTCLOCK<= sysclock2;
  
  --**********************************************  
  --GENERATE DATA_RDY  SIGNAL FOR TEST
  
  GenerateReadyPulse: PROCESS 													    
  begin
    wait for 5000 us;
    ready<= '1';     
    wait for 100 us;
    ready<= '0';
  end process GenerateReadyPulse;
  DATA_RDY <= ready;	
  --********************************************** 
  
  
  --GENERATE DSP Serial read		
  WriteData: PROCESS 													    	
  begin
    wait until falling_edge(CS_n);			
    
    for I in 0 to 31 loop
      if CS_n = '0' then
        wait until falling_edge(SCLK);	
      end if;
    end loop;
    
    for I2 in 0 to 23 loop
      if CS_n = '0' then

        wait until rising_edge(SCLK);
        DATA_FROM_AD <= DATA_test(I2); 
      end if;	
    end loop;			
    
    
  end process WriteData;
  
  
END ARCHITECTURE RTL;
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