-- VHDL Entity PERSONALITY_FPGA.HOSTPORT.symbol
--
-- Created:
--          by - DearyJ.UNKNOWN (DEARY-JUSTIN)
--          at - 07:47:42 11/30/2006
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2005.3 (Build 75)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY HOSTPORT IS
   PORT( 
      ADR1       : IN     std_logic;
      ADR2       : IN     std_logic;
      ADR3       : IN     std_logic;
      CLK        : IN     std_logic;
      CS9_n      : IN     std_logic;
      HINT_DSP_n : IN     std_logic;
      HRDY_DSP_n : IN     std_logic;
      R_W        : IN     std_logic;
      BCS9_n     : OUT    std_logic;
      DSACK1     : OUT    std_logic;
      HCNTL0_DSP : OUT    std_logic;
      HCNTL1_DSP : OUT    std_logic;
      HHWIL_DSP  : OUT    std_logic;
      IRQ5       : OUT    std_logic
   );

-- Declarations

END HOSTPORT ;

--
-- VHDL Architecture PERSONALITY_FPGA.HOSTPORT.struct
--
-- Created:
--          by - DearyJ.UNKNOWN (DEARY-JUSTIN)
--          at - 07:47:42 11/30/2006
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2005.3 (Build 75)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ARCHITECTURE struct OF HOSTPORT IS

   -- Architecture declarations

   -- Internal signal declarations
   SIGNAL W_R      : std_logic;
   SIGNAL din0     : std_logic;
   SIGNAL din2     : std_logic;
   SIGNAL dout2    : std_logic;
   SIGNAL q        : std_logic;
   SIGNAL q1       : std_logic;
   SIGNAL q2       : std_logic;
   SIGNAL q4667    : std_logic;
   SIGNAL setshift : std_logic;

   -- Implicit buffer signal declarations
   SIGNAL DSACK1_internal : std_logic;


   -- ModuleWare signal declarations(v1.7) for instance 'I11' of 'adff'
   SIGNAL mw_I11reg_cval : std_logic;

   -- ModuleWare signal declarations(v1.7) for instance 'I13' of 'adff'
   SIGNAL mw_I13reg_cval : std_logic;

   -- ModuleWare signal declarations(v1.7) for instance 'I14' of 'adff'
   SIGNAL mw_I14reg_cval : std_logic;

   -- ModuleWare signal declarations(v1.7) for instance 'I16' of 'adff'
   SIGNAL mw_I16reg_cval : std_logic;


BEGIN

   -- ModuleWare code(v1.7) for instance 'I11' of 'adff'
   q4667 <= mw_I11reg_cval;
   i11seq_proc: PROCESS (CLK, setshift)
   BEGIN
      IF (setshift = '1' OR setshift = 'H') THEN
         mw_I11reg_cval <= '1';
      ELSIF (CLK'EVENT AND CLK='1') THEN
         mw_I11reg_cval <= dout2;
      END IF;
   END PROCESS i11seq_proc;

   -- ModuleWare code(v1.7) for instance 'I13' of 'adff'
   q1 <= mw_I13reg_cval;
   i13seq_proc: PROCESS (CLK, setshift)
   BEGIN
      IF (setshift = '1' OR setshift = 'H') THEN
         mw_I13reg_cval <= '1';
      ELSIF (CLK'EVENT AND CLK='1') THEN
         mw_I13reg_cval <= q4667;
      END IF;
   END PROCESS i13seq_proc;

   -- ModuleWare code(v1.7) for instance 'I14' of 'adff'
   q2 <= mw_I14reg_cval;
   i14seq_proc: PROCESS (CLK, setshift)
   BEGIN
      IF (setshift = '1' OR setshift = 'H') THEN
         mw_I14reg_cval <= '1';
      ELSIF (CLK'EVENT AND CLK='1') THEN
         mw_I14reg_cval <= q1;
      END IF;
   END PROCESS i14seq_proc;

   -- ModuleWare code(v1.7) for instance 'I16' of 'adff'
   q <= mw_I16reg_cval;
   i16seq_proc: PROCESS (CLK, setshift)
   BEGIN
      IF (setshift = '1' OR setshift = 'H') THEN
         mw_I16reg_cval <= '1';
      ELSIF (CLK'EVENT AND CLK='1') THEN
         mw_I16reg_cval <= q2;
      END IF;
   END PROCESS i16seq_proc;

   -- ModuleWare code(v1.7) for instance 'I7' of 'and'
   BCS9_n <= din0 AND din2;

   -- ModuleWare code(v1.7) for instance 'I0' of 'buff'
   HHWIL_DSP <= ADR1;

   -- ModuleWare code(v1.7) for instance 'I1' of 'buff'
   HCNTL1_DSP <= ADR3;

   -- ModuleWare code(v1.7) for instance 'I2' of 'buff'
   HCNTL0_DSP <= ADR2;

   -- ModuleWare code(v1.7) for instance 'I15' of 'gnd'
   dout2 <= '0';

   -- ModuleWare code(v1.7) for instance 'I3' of 'inv'
   W_R <= NOT(R_W);

   -- ModuleWare code(v1.7) for instance 'I6' of 'inv'
   DSACK1_internal <= NOT(q);

   -- ModuleWare code(v1.7) for instance 'I8' of 'inv'
   IRQ5 <= NOT(HINT_DSP_n);

   -- ModuleWare code(v1.7) for instance 'I18' of 'or'
   setshift <= CS9_n OR HRDY_DSP_n;

   -- ModuleWare code(v1.7) for instance 'I19' of 'or'
   din0 <= CS9_n OR W_R;

   -- ModuleWare code(v1.7) for instance 'I20' of 'or'
   din2 <= R_W OR CS9_n OR DSACK1_internal;

   -- Instance port mappings.

   -- Implicit buffered output assignments
   DSACK1 <= DSACK1_internal;

END struct;