--
-- VHDL Architecture PERSONALITY_FPGA_lib.pwm_cntrl_tester.rtl
--
-- Created:
--          by - DearyJ.UNKNOWN (DEARY-JUSTIN)
--          at - 15:15:41 09/26/2006
--
-- using Mentor Graphics HDL Designer(TM) 2004.1a (Build 15)
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY pwm_cntrl_tester IS
   PORT( 
      PWMOUT         : IN     STD_LOGIC;
      CLOCK          : OUT    STD_LOGIC;
      DATARDY        : OUT    STD_LOGIC;
      PWM_DCYCLE_CNT : OUT    STD_LOGIC_VECTOR (15 DOWNTO 0);
      PWM_FREQ_CNT   : OUT    STD_LOGIC_VECTOR (15 DOWNTO 0);
      RESET          : OUT    STD_LOGIC
   );

-- Declarations

END pwm_cntrl_tester ;

--
ARCHITECTURE rtl OF pwm_cntrl_tester IS
signal sysclock	 :	std_logic := '1';
signal ready	:	std_logic := '0';
signal cv_test	:	unsigned (15 DOWNTO 0) :=B"0100_0000_0000_0000" ; 

	BEGIN

   
	-- GENERATE SYSTEM RESET
	 RESET <= '0', '1' after 100 ns, '0' after 1000 ns;

	--GENERATE CLOCK SIGNAL FOR TEST											     
	 sysclock <= not sysclock after 111 ns;         -- 4.5Mhz  for circuit with divide
	 CLOCK <= sysclock;
  
  
--**********************************************  
    --GENERATE DATA_RDY  SIGNAL FOR TEST

 	GenerateReadyPulse: PROCESS 													    
	   	begin
	   	wait for 50 ms;
			cv_test<= cv_test + B"0001_0000_0000_0000";   
			wait for 100 ms;
			ready<= '1'; 						    
			wait for 100 us;
			ready<= '0';			
	 end process GenerateReadyPulse;
			DATARDY <= ready;	
			PWM_FREQ_CNT <= B"1000_0000_0000_0000";
			PWM_DCYCLE_CNT <= STD_LOGIC_VECTOR(cv_test);
--********************************************** 
END ARCHITECTURE rtl;