-- VHDL Entity PERSONALITY_FPGA.QSPI.symbol
--
-- Created:
--          by - DearyJ.UNKNOWN (DEARY-JUSTIN)
--          at - 07:47:41 11/30/2006
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2005.3 (Build 75)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY QSPI IS
   PORT( 
      BQSPI_DSP_DATA2CPU  : IN     std_logic;
      BQSPI_PER_DATA2CPU  : IN     std_logic;
      BQSPI_TEMP_DATA2CPU : IN     std_logic;
      PCS_n               : IN     std_logic_vector (2 DOWNTO 0);
      PCS_n_bit3          : IN     std_logic;
      QSPI_CLK            : IN     std_logic;
      QSPI_CS_EN          : IN     std_logic;
      QSPI_DO             : IN     std_logic;
      BQSPI_CLK           : OUT    std_logic;
      BQSPI_CLK_TEMP      : OUT    std_logic;
      BQSPI_DOUT          : OUT    std_logic;
      BQSPI_DOUT_TEMP     : OUT    std_logic;
      BQSPI_DSP_CS_n      : OUT    std_logic;
      BQSPI_PER_CS_n      : OUT    std_logic;
      BQSPI_TEMP_CS_n     : OUT    std_logic;
      QSPI_DI_n           : OUT    std_logic
   );

-- Declarations

END QSPI ;

--
-- VHDL Architecture PERSONALITY_FPGA.QSPI.struct
--
-- Created:
--          by - DearyJ.UNKNOWN (DEARY-JUSTIN)
--          at - 07:47:42 11/30/2006
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2005.3 (Build 75)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

LIBRARY PERSONALITY_FPGA;

ARCHITECTURE struct OF QSPI IS

   -- Architecture declarations

   -- Internal signal declarations
   SIGNAL Y     : std_logic_vector(7 DOWNTO 0);
   SIGNAL din1  : std_logic;
   SIGNAL dout  : std_logic;
   SIGNAL dout1 : std_logic;
   SIGNAL dout3 : std_logic;
   SIGNAL dout4 : std_logic;

   -- Implicit buffer signal declarations
   SIGNAL BQSPI_CLK_internal  : std_logic;
   SIGNAL BQSPI_DOUT_internal : std_logic;


   -- Component Declarations
   COMPONENT DECODER
   PORT (
      EN0 : IN     std_logic;
      EN1 : IN     std_logic;
      EN2 : IN     std_logic;
      I   : IN     std_logic_vector (2 DOWNTO 0);
      Y   : OUT    std_logic_vector (7 DOWNTO 0)
   );
   END COMPONENT;

   -- Optional embedded configurations
   -- pragma synthesis_off
   FOR ALL : DECODER USE ENTITY PERSONALITY_FPGA.DECODER;
   -- pragma synthesis_on


BEGIN

   -- ModuleWare code(v1.7) for instance 'I3' of 'and'
   dout <= Y(5) AND BQSPI_TEMP_DATA2CPU;

   -- ModuleWare code(v1.7) for instance 'I14' of 'and'
   dout1 <= Y(4) AND BQSPI_DSP_DATA2CPU;

   -- ModuleWare code(v1.7) for instance 'I16' of 'and'
   dout3 <= Y(2) AND BQSPI_PER_DATA2CPU;

   -- ModuleWare code(v1.7) for instance 'I2' of 'buff'
   BQSPI_CLK_internal <= QSPI_CLK;

   -- ModuleWare code(v1.7) for instance 'I10' of 'buff'
   BQSPI_DOUT_internal <= QSPI_DO;

   -- ModuleWare code(v1.7) for instance 'I5' of 'inv'
   BQSPI_PER_CS_n <= NOT(Y(2));

   -- ModuleWare code(v1.7) for instance 'I7' of 'inv'
   BQSPI_DSP_CS_n <= NOT(Y(4));

   -- ModuleWare code(v1.7) for instance 'I8' of 'inv'
   BQSPI_TEMP_CS_n <= NOT(Y(5));

   -- ModuleWare code(v1.7) for instance 'I18' of 'inv'
   dout4 <= NOT(PCS_n_bit3);

   -- ModuleWare code(v1.7) for instance 'I9' of 'nor'
   din1 <= NOT(Y(0) OR Y(1) OR Y(2) OR Y(3) OR Y(4));

   -- ModuleWare code(v1.7) for instance 'I11' of 'or'
   QSPI_DI_n <= NOT(dout OR dout1 OR dout3);

   -- ModuleWare code(v1.7) for instance 'I12' of 'tribuf'
   i12combo_proc: PROCESS (BQSPI_CLK_internal, din1)
   BEGIN
      IF (din1 = '0' OR din1 = 'L') THEN
         BQSPI_CLK_TEMP <= 'Z';
      ELSIF (din1 = '1' OR din1 = 'H') THEN
         BQSPI_CLK_TEMP <= BQSPI_CLK_internal;
      ELSE
         BQSPI_CLK_TEMP <= 'X';
      END IF;
   END PROCESS i12combo_proc;

   -- ModuleWare code(v1.7) for instance 'I13' of 'tribuf'
   i13combo_proc: PROCESS (BQSPI_DOUT_internal, din1)
   BEGIN
      IF (din1 = '0' OR din1 = 'L') THEN
         BQSPI_DOUT_TEMP <= 'Z';
      ELSIF (din1 = '1' OR din1 = 'H') THEN
         BQSPI_DOUT_TEMP <= BQSPI_DOUT_internal;
      ELSE
         BQSPI_DOUT_TEMP <= 'X';
      END IF;
   END PROCESS i13combo_proc;

   -- Instance port mappings.
   I6 : DECODER
      PORT MAP (
         I   => PCS_n,
         EN1 => QSPI_CS_EN,
         EN2 => dout4,
         EN0 => dout4,
         Y   => Y
      );

   -- Implicit buffered output assignments
   BQSPI_CLK  <= BQSPI_CLK_internal;
   BQSPI_DOUT <= BQSPI_DOUT_internal;

END struct;