--
-- VHDL Architecture PLD_2998_lib.refmachine_tester.arch_name
--
-- Created:
--          by - dearyj.UNKNOWN (DEARY-JUSTIN)
--          at - 11:12:13 08/26/2004
--
-- using Mentor Graphics HDL Designer(TM) 2004.1a (Build 15)
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;


ENTITY refmachine_tester IS
   PORT( 
      CLOCK         : OUT    STD_LOGIC;
      RESET         : OUT    STD_LOGIC;
      REF_START_EXP : OUT    STD_LOGIC;
      AD_SPI_DO     : OUT    STD_LOGIC;
      AD_BUSY       : OUT    STD_LOGIC;
      DSP_SPI_SCLK  : OUT    STD_LOGIC;
      DSP_SPI_CS    : OUT    STD_LOGIC;
      AD_SPI_SCLK   : IN     STD_LOGIC;
      AD_SPI_CS     : IN     STD_LOGIC;
      DSP_SPI_DI    : IN     STD_LOGIC;
      START_REF_DSP : IN     STD_LOGIC
   );

-- Declarations

END refmachine_tester ;

--


ARCHITECTURE RTL OF refmachine_tester IS
SIGNAL REF_SIGNAL	:	std_logic_vector (17 downto 0):= "000000000000011001";
SIGNAL REF_ERROR	:	std_logic_vector (17 downto 0):= "000000000000001011";
SIGNAL DataFromAD   :	std_logic_vector (35 downto 0); 

signal busy		    :	std_logic := '0';
signal sysclock	 :	std_logic := '1';
signal ref_start	:	std_logic := '0';
 



	BEGIN

   
	-- GENERATE SYSTEM RESET
	RESET <= '0', '1' after 5 ns, '0' after 100 ns;

	--GENERATE CLOCK SIGNAL FOR TEST											     
	 sysclock <= not sysclock after 13.875013875 ns;         -- 36.036Mhz  for circuit with divide
	 CLOCK <= sysclock;

  	--GENERATE REFERENCE START SIGNAL FOR TEST											     
	 ref_start <= not ref_start after 200 us;   
	 REF_START_EXP <= ref_start;


 
 	 --GENERATE DSP Serial read		
 	 GenerateDSPserial: PROCESS 													    
	   	 begin
			 wait until rising_edge(ref_start);	   -- wait first exposure
 			 wait until rising_edge(ref_start);	   -- wait second exposure
			 wait until rising_edge(ref_start);	   -- wait third exposure
			 wait until rising_edge(ref_start); 	   -- wait fourth exposure (end of sample, so perform read)
 
			 wait for 15 us;	     -- meets 7us timming
 
			 DSP_SPI_CS <= '0';
 			 wait for 2 us;
	    
 			DSP_SPI_SCLK <= '1';  	wait for 1 us;		
 			DSP_SPI_SCLK <= '0';	  wait for 1 us;
 			DSP_SPI_SCLK <= '1';  	wait for 1 us;		
 			DSP_SPI_SCLK <= '0';  	wait for 1 us; 
			DSP_SPI_SCLK <= '1';  	wait for 1 us;
 			DSP_SPI_SCLK <= '0';	  wait for 1 us;
			DSP_SPI_SCLK <= '1';  	wait for 1 us;
 			DSP_SPI_SCLK <= '0';	  wait for 1 us;
			DSP_SPI_SCLK <= '1';  	wait for 1 us;
 			DSP_SPI_SCLK <= '0';	  wait for 1 us;
			DSP_SPI_SCLK <= '1';  	wait for 1 us;
 			DSP_SPI_SCLK <= '0';	  wait for 1 us;
			DSP_SPI_SCLK <= '1';  	wait for 1 us;
 			DSP_SPI_SCLK <= '0';	  wait for 1 us;
			DSP_SPI_SCLK <= '1';  	wait for 1 us;
 			DSP_SPI_SCLK <= '0';	  wait for 1 us;

			DSP_SPI_SCLK <= '1';  	wait for 1 us;
 			DSP_SPI_SCLK <= '0';	  wait for 1 us;
			DSP_SPI_SCLK <= '1';  	wait for 1 us;
 			DSP_SPI_SCLK <= '0';	  wait for 1 us;
			DSP_SPI_SCLK <= '1';  	wait for 1 us;
 			DSP_SPI_SCLK <= '0';	  wait for 1 us;
			DSP_SPI_SCLK <= '1';  	wait for 1 us;
 			DSP_SPI_SCLK <= '0';	  wait for 1 us;
			DSP_SPI_SCLK <= '1';  	wait for 1 us;
 			DSP_SPI_SCLK <= '0';	  wait for 1 us;
			DSP_SPI_SCLK <= '1';  	wait for 1 us;
 			DSP_SPI_SCLK <= '0';	  wait for 1 us;
			DSP_SPI_SCLK <= '1';  	wait for 1 us;
 			DSP_SPI_SCLK <= '0';	  wait for 1 us;
			DSP_SPI_SCLK <= '1';  	wait for 1 us;
 			DSP_SPI_SCLK <= '0';	  wait for 1 us;

 			DSP_SPI_SCLK <= '1';  	wait for 1 us;		
 			DSP_SPI_SCLK <= '0';	  wait for 1 us;
 			DSP_SPI_SCLK <= '1';  	wait for 1 us;		
 			DSP_SPI_SCLK <= '0';	  wait for 1 us; 
			DSP_SPI_SCLK <= '1';  	wait for 1 us;
 			DSP_SPI_SCLK <= '0';	  wait for 1 us;
			DSP_SPI_SCLK <= '1';  	wait for 1 us;
 			DSP_SPI_SCLK <= '0';	  wait for 1 us;
			DSP_SPI_SCLK <= '1';  	wait for 1 us;
 			DSP_SPI_SCLK <= '0';  	wait for 1 us;
			DSP_SPI_SCLK <= '1';  	wait for 1 us;
 			DSP_SPI_SCLK <= '0';	  wait for 1 us;
			DSP_SPI_SCLK <= '1';  	wait for 1 us;
 			DSP_SPI_SCLK <= '0';  	wait for 1 us;
			DSP_SPI_SCLK <= '1';  	wait for 1 us;
 			DSP_SPI_SCLK <= '0';	  wait for 1 us;

			DSP_SPI_SCLK <= '1';  	wait for 1 us;
 			DSP_SPI_SCLK <= '0';	  wait for 1 us;
			DSP_SPI_SCLK <= '1';  	wait for 1 us;
 			DSP_SPI_SCLK <= '0';	  wait for 1 us;
			DSP_SPI_SCLK <= '1';  	wait for 1 us;
 			DSP_SPI_SCLK <= '0';	  wait for 1 us;
			DSP_SPI_SCLK <= '1';  	wait for 1 us;
 			DSP_SPI_SCLK <= '0';	  wait for 1 us;
			DSP_SPI_SCLK <= '1';  	wait for 1 us;
 			DSP_SPI_SCLK <= '0';	  wait for 1 us;
			DSP_SPI_SCLK <= '1';  	wait for 1 us;
 			DSP_SPI_SCLK <= '0';	  wait for 1 us;
			DSP_SPI_SCLK <= '1';  	wait for 1 us;
 			DSP_SPI_SCLK <= '0';   wait for 1 us;
			DSP_SPI_SCLK <= '1';  	wait for 1 us;
 			DSP_SPI_SCLK <= '0';  	wait for 1 us;

			DSP_SPI_CS <= '1';

	 end process GenerateDSPserial;
  		


  
    --GENERATE BUSY  SIGNAL FOR TEST

 	GenerateBusyPulse: PROCESS 													    
	   	begin
			wait until rising_edge(ref_start);
			wait for 100 ns;
			busy<= '1';     --Read signal
			wait for 1.5 us;
			busy<= '0';
			wait for 3.55 us;			
			busy<= '1';	   --Read Error
			wait for 1.5 us;
			busy<= '0';
	 end process GenerateBusyPulse;
  			AD_BUSY<= busy;
  			



    	--GENERATE AD_SPI_DO  SIGNAL FOR TEST
	DataFromAD <= (REF_SIGNAL & REF_ERROR);
 	GenerateAD_SPI_Do: PROCESS(AD_SPI_SCLK,DataFromAD,ref_start ) 	
		VARIABLE i 			: 	integer range 0 TO 37;										    
	   	begin
					if (ref_start='0')then
						i := 0;

					elsif falling_edge(AD_SPI_SCLK) then				
						i := i+1;
						AD_SPI_DO <= DataFromAD(36-i);
					   	if (i > 35) then
							i := 35;
						end if;
					end if;					       

	 end process GenerateAD_SPI_Do;

  
END ARCHITECTURE RTL;