-- VHDL Entity PERSONALITY_FPGA.top_level.symbol -- -- Created: -- by - DearyJ.UNKNOWN (DEARY-JUSTIN) -- at - 15:45:49 02/ 5/2007 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2005.3 (Build 75) -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY top_level IS PORT( ADD10 : IN std_logic; ADR : IN std_logic_vector (5 DOWNTO 0); AUTOZERO : IN std_logic; BQSPI_DSP_DATA2CPU : IN std_logic; BQSPI_PER_DATA2CPU : IN std_logic; BQSPI_TEMP_DATA2CPU : IN std_logic; BSPI_CLKX0 : IN STD_LOGIC; BSPI_FSX0 : IN STD_LOGIC; CE_ADC_PAR_READ_n : IN std_logic; CHARTMARK : IN std_logic; CLOCK : IN std_logic; COLUMN_STRB_n : IN std_logic; CS5_n : IN std_logic; CS8_n : IN std_logic; CS9_n : IN std_logic; DEBUG1 : IN std_logic; addr6 : IN std_logic; DOUT_THERM : IN std_logic; DRDY_THERM_n : IN std_logic; EMIFDATA_IN : IN std_logic_vector (7 DOWNTO 0); EOS : IN std_logic; FUSE_15V : IN std_logic; FUSE_24V : IN std_logic; HINT_DSP_n : IN std_logic; HRDY_DSP_n : IN std_logic; INJECTSTART : IN std_logic; LAMPONOFF : IN std_logic; LAMP_LIT_n : IN std_logic; LEAK_DET_PRESENT_n : IN std_logic; PCS_n : IN std_logic_vector (2 DOWNTO 0); PCS_n_bit3 : IN std_logic; PDABUSY : IN std_logic; QSPI_CLK : IN std_logic; QSPI_DO : IN std_logic; RD_WR : IN std_logic; REFBUSY : IN STD_LOGIC; REFSDATA : IN STD_LOGIC; RESET_n : IN std_logic; RMTVCC_FUSE : IN std_logic; TIN0_DSP : IN std_logic; TOUT0_DSP : IN STD_LOGIC; TOUT1_DSP : IN std_logic; TPUBUS : IN std_logic_vector (14 DOWNTO 9); TPUBUS1 : IN std_logic; TPUBUS7 : IN std_logic; A0_BYTE : OUT std_logic; A1_BYTE : OUT std_logic; BBCS9_n : OUT std_logic; BCS9_n : OUT std_logic; BQSPI_CLK : OUT std_logic; BQSPI_CLK_TEMP : OUT std_logic; BQSPI_DOUT : OUT std_logic; BQSPI_DOUT_TEMP : OUT std_logic; BQSPI_DSP_CS_n : OUT std_logic; BQSPI_PER_CS_n : OUT std_logic; BQSPI_TEMP_CS_n : OUT std_logic; BSPI_DR0 : OUT STD_LOGIC; B_DATA_CS_n : OUT std_logic; CS_DAC1_n : OUT std_logic; CS_DAC2_n : OUT std_logic; CS_THERM_n : OUT std_logic; DIN_THERM : OUT std_logic; DSACK1 : OUT std_logic; DSP_SOFTWARE_RST_n : OUT std_logic := '0'; EMIFDATA_OUT : OUT std_logic_vector (7 DOWNTO 0); EVENT_OUT1 : OUT std_logic; EVENT_OUT2 : OUT std_logic; EXT_INT_IO_4_DSP : OUT std_logic; EXT_INT_IO_5_DSP : OUT std_logic; EXT_INT_IO_6_DSP : OUT std_logic; EXT_INT_IO_7_DSP : OUT std_logic; FAN_PWM : OUT std_logic; FLTR_STRB : OUT std_logic; FLTR_WHL_DIR : OUT std_logic; FLTR_WHL_EN : OUT std_logic := '1'; FLTR_WHL_HOLD : OUT std_logic := '1'; FLTR_WHL_RST : OUT std_logic; FLTR_WHL_STEP : OUT std_logic; GP2 : OUT std_logic; HCNTL0_DSP : OUT std_logic; HCNTL1_DSP : OUT std_logic; HEATER_PWM : OUT std_logic; HHWIL_DSP : OUT std_logic; IRQ5 : OUT std_logic; LAMP_ON : OUT std_logic := '0'; LED_LOOP_STRB : OUT std_logic; MEM_CS_n : OUT std_logic; PER_AD_CLK : OUT std_logic; QSPI_DI_n : OUT std_logic; READ_PDA_n : OUT std_logic; REFCS_n : OUT STD_LOGIC; REFSCLK : OUT STD_LOGIC; R_W_BUF : OUT std_logic := '0'; SCLK_DAC_1 : OUT std_logic; SCLK_DAC_2 : OUT std_logic; SCLK_THERM : OUT std_logic; SDIO_DAC_1 : OUT std_logic; SDIO_DAC_2 : OUT std_logic; SEL_EN : OUT std_logic; START_PDA_DSP : OUT std_logic; START_REF_DSP : OUT STD_LOGIC; STAT_GRN : OUT std_logic; STAT_RED : OUT std_logic; TPUBUS8 : OUT std_logic; TRI_REG : OUT std_logic; W_R_BUF : OUT std_logic := '0'; DATA : INOUT std_logic_vector (15 DOWNTO 8); CS4_n : IN std_logic; UB_GPU : OUT std_logic; LB_GPU : OUT std_logic ); -- Declarations -- Declarations -- VHDL Attribute Template --attribute of : is ; attribute pin_number : string ; type exemplar_string_array is array (natural range <>, natural range <>) of character ; attribute array_pin_number : exemplar_string_array ; attribute pin_number of ADD10 : signal is "18"; attribute array_pin_number of ADR : signal is ("14","40","41","44","45","46") ; attribute pin_number of AUTOZERO: signal is "184"; attribute pin_number of BQSPI_DSP_DATA2CPU: signal is "54"; attribute pin_number of BQSPI_PER_DATA2CPU: signal is "28"; attribute pin_number of BQSPI_TEMP_DATA2CPU: signal is "24"; attribute pin_number of BSPI_CLKX0: signal is "128"; attribute pin_number of BSPI_FSX0: signal is "131"; attribute pin_number of CE_ADC_PAR_READ_n: signal is "132"; attribute pin_number of CHARTMARK: signal is "78"; attribute pin_number of CLOCK : signal is "79"; attribute pin_number of COLUMN_STRB_n: signal is "95"; attribute pin_number of CS5_n: signal is "30"; attribute pin_number of CS8_n : signal is "148"; attribute pin_number of CS9_n: signal is "29"; attribute pin_number of DEBUG1: signal is "25"; attribute pin_number of DOUT_THERM: signal is "166"; attribute pin_number of DRDY_THERM_n : signal is "208"; attribute array_pin_number of EMIFDATA_IN : signal is ("89","88","87","86","94","93","92","90") ; attribute pin_number of EOS: signal is "119"; attribute pin_number of FUSE_15V : signal is "206"; attribute pin_number of FUSE_24V : signal is "187"; attribute pin_number of HINT_DSP_n: signal is "83"; attribute pin_number of HRDY_DSP_n: signal is "80"; attribute pin_number of INJECTSTART: signal is "136"; attribute pin_number of LAMPONOFF: signal is "182"; attribute pin_number of LAMP_LIT_n: signal is "142"; attribute pin_number of LEAK_DET_PRESENT_n : signal is "204"; attribute array_pin_number of PCS_n : signal is ("38","37","36") ; attribute pin_number of PCS_n_bit3: signal is "39"; attribute pin_number of PDABUSY: signal is "121"; attribute pin_number of QSPI_CLK: signal is "126"; attribute pin_number of QSPI_DO: signal is "122"; attribute pin_number of RD_WR: signal is "31"; attribute pin_number of REFBUSY: signal is "120"; attribute pin_number of REFSDATA: signal is "139"; attribute pin_number of RESET_n: signal is "180"; attribute pin_number of RMTVCC_FUSE: signal is "189"; attribute pin_number of TIN0_DSP: signal is "175"; attribute pin_number of TOUT0_DSP: signal is "197"; attribute pin_number of TOUT1_DSP: signal is "195"; attribute array_pin_number of TPUBUS : signal is ("205","203","202","200","199","198") ; attribute pin_number of TPUBUS1: signal is "176"; attribute pin_number of TPUBUS7: signal is "193"; attribute pin_number of A0_BYTE: signal is "112"; attribute pin_number of A1_BYTE: signal is "111"; attribute pin_number of BBCS9_n: signal is "47"; attribute pin_number of BCS9_n: signal is "27"; attribute pin_number of BQSPI_CLK: signal is "127"; attribute pin_number of BQSPI_CLK_TEMP: signal is "11"; attribute pin_number of BQSPI_DOUT: signal is "125"; attribute pin_number of BQSPI_DOUT_TEMP: signal is "17"; attribute pin_number of BQSPI_DSP_CS_n: signal is "55"; attribute pin_number of BQSPI_PER_CS_n: signal is "7"; attribute pin_number of BQSPI_TEMP_CS_n: signal is "143"; attribute pin_number of BSPI_DR0: signal is "135"; attribute pin_number of B_DATA_CS_n: signal is "53"; attribute pin_number of CS_DAC1_n: signal is "159"; attribute pin_number of CS_DAC2_n: signal is "164"; attribute pin_number of CS_THERM_n: signal is "134"; attribute pin_number of DIN_THERM: signal is "85"; attribute pin_number of DSACK1 : signal is "26"; attribute pin_number of DSP_SOFTWARE_RST_n: signal is "160"; attribute array_pin_number of EMIFDATA_OUT : signal is ("96","97","99","100","101","102","103","104") ; attribute pin_number of EVENT_OUT1: signal is "163"; attribute pin_number of EVENT_OUT2: signal is "167"; attribute pin_number of EXT_INT_IO_4_DSP : signal is "71"; attribute pin_number of EXT_INT_IO_5_DSP : signal is "70"; attribute pin_number of EXT_INT_IO_6_DSP : signal is "69"; attribute pin_number of EXT_INT_IO_7_DSP : signal is "68"; attribute pin_number of FAN_PWM : signal is "144"; attribute pin_number of FLTR_STRB : signal is "8"; attribute pin_number of FLTR_WHL_DIR: signal is "172"; attribute pin_number of FLTR_WHL_EN: signal is "168"; attribute pin_number of FLTR_WHL_HOLD: signal is "170"; attribute pin_number of FLTR_WHL_RST: signal is "169"; attribute pin_number of FLTR_WHL_STEP: signal is "173"; attribute pin_number of GP2: signal is "177"; attribute pin_number of HCNTL0_DSP : signal is "73"; attribute pin_number of HCNTL1_DSP : signal is "74"; attribute pin_number of HEATER_PWM : signal is "147"; attribute pin_number of HHWIL_DSP : signal is "75"; attribute pin_number of IRQ5: signal is "15"; attribute pin_number of LAMP_ON: signal is "150"; attribute pin_number of LED_LOOP_STRB : signal is "9"; attribute pin_number of MEM_CS_n: signal is "174"; attribute pin_number of PER_AD_CLK: signal is "196"; attribute pin_number of QSPI_DI_n: signal is "133"; attribute pin_number of READ_PDA_n: signal is "113"; attribute pin_number of REFCS_n: signal is "141"; attribute pin_number of REFSCLK: signal is "140"; attribute pin_number of R_W_BUF: signal is "149"; attribute pin_number of SCLK_DAC_1: signal is "158"; attribute pin_number of SCLK_DAC_2: signal is "162"; attribute pin_number of SCLK_THERM: signal is "179"; attribute pin_number of SDIO_DAC_1: signal is "157"; attribute pin_number of SDIO_DAC_2: signal is "161"; attribute pin_number of SEL_EN: signal is "115"; attribute pin_number of START_PDA_DSP: signal is "114"; attribute pin_number of START_REF_DSP: signal is "116"; attribute pin_number of STAT_GRN: signal is "190"; attribute pin_number of STAT_RED: signal is "191"; attribute pin_number of TPUBUS8: signal is "67"; attribute pin_number of TRI_REG: signal is "13"; attribute pin_number of W_R_BUF: signal is "12"; attribute array_pin_number of DATA : signal is ("65","64","63","61","60","58","57","56") ; END top_level ; -- -- VHDL Architecture PERSONALITY_FPGA.top_level.struct -- -- Created: -- by - DearyJ.UNKNOWN (DEARY-JUSTIN) -- at - 15:45:50 02/ 5/2007 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2005.3 (Build 75) -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; USE ieee.numeric_std.all; LIBRARY PERSONALITY_FPGA; ARCHITECTURE struct OF top_level IS -- Architecture declarations -- Internal signal declarations SIGNAL DISABLE_THERM : std_logic; SIGNAL RESET : std_logic; SIGNAL FILTER_EN_n : std_logic := '1'; SIGNAL FILTER_HOLD_n : std_logic := '1'; SIGNAL AUTOZERO_ALEVEL : std_logic; SIGNAL AUTOZERO_EN : std_logic; SIGNAL CHARTMARK_ALEVEL : std_logic; SIGNAL W_STROBE : std_logic; SIGNAL CHARTMARK_EN : std_logic; SIGNAL R_STROBE : std_logic; SIGNAL DATA_CH1 : STD_LOGIC_VECTOR(23 DOWNTO 0); SIGNAL INJECTSTART_ALEVEL : std_logic; SIGNAL DATA_CH0 : STD_LOGIC_VECTOR(23 DOWNTO 0); SIGNAL INJECTSTART_EN : std_logic; SIGNAL LAMPONOFF_ALEVEL : std_logic; SIGNAL PWM2_DCYCLE_CNT : STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL LAMPONOFF_EN : std_logic; SIGNAL PWM2_FREQ_CNT : STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL DAC1_DATA : std_logic_vector(31 DOWNTO 0); SIGNAL DAC2_DATA : std_logic_vector(31 DOWNTO 0); SIGNAL CLOCK9MHZ : std_logic; SIGNAL CPU2000_ALEVEL : std_logic; SIGNAL CPU2000_EN : std_logic; SIGNAL SPI_ENABLE : std_logic; SIGNAL PIDRST : std_logic; SIGNAL DATA_RDY_SYNC : STD_LOGIC; SIGNAL DEBUG_MODE : std_logic; SIGNAL W_REG_00005 : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL CLOCK18MHZ : std_logic; SIGNAL CLOCK1125KHZ : std_logic; SIGNAL W_REG_00006 : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL DACSENDCMD : STD_LOGIC; SIGNAL W_REG_00007 : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL W_REG_00010 : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL W_REG_00011 : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL W_REG_00012 : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL W_REG_00015 : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL DSP_RST_STRB : STD_LOGIC; SIGNAL CLOCK281KHZ : std_logic; SIGNAL do4 : std_logic; SIGNAL BCS5_n : STD_LOGIC; SIGNAL do5 : std_logic; SIGNAL do0 : std_logic; SIGNAL W_REG_00019 : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL CLOCK70KHZ : std_logic; SIGNAL CLOCK4_5MHZ : std_logic; SIGNAL do1 : std_logic; SIGNAL do2 : std_logic; SIGNAL q : std_logic; -- Template for Synopsys DC constraints -- pragma dc_script_begin -- -- pragma dc_script_end -- -- VHDL Attribute Template --attribute of : is ; attribute pin_number of PDABUSY: signal is "95"; SIGNAL BUSY : std_logic; -- Template for Synopsys DC constraints -- pragma dc_script_begin -- -- pragma dc_script_end -- -- VHDL Attribute Template --attribute of : is ; attribute pin_number of PDABUSY: signal is "95"; SIGNAL do3 : std_logic; SIGNAL R_REG_00008 : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL R_REG_00009 : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL dout : std_logic; SIGNAL dout1 : std_logic; SIGNAL dout2 : std_logic; SIGNAL dout3 : STD_LOGIC; SIGNAL dout4 : std_logic; SIGNAL do6 : std_logic; -- Implicit buffer signal declarations SIGNAL EXT_INT_IO_7_DSP_internal : std_logic; SIGNAL PER_AD_CLK_internal : std_logic; SIGNAL HEATER_PWM_internal : std_logic; -- ModuleWare signal declarations(v1.7) for instance 'I12' of 'adff' SIGNAL mw_I12reg_cval : std_logic; -- ModuleWare signal declarations(v1.7) for instance 'I16' of 'adff' SIGNAL mw_I16reg_cval : std_logic; -- ModuleWare signal declarations(v1.7) for instance 'I22' of 'clkdiv' SIGNAL mw_I22reg_cval : INTEGER RANGE 0 TO 1; SIGNAL mw_I22reg_nval : INTEGER RANGE 0 TO 1; -- ModuleWare signal declarations(v1.7) for instance 'I28' of 'clkdiv' SIGNAL mw_I28reg_cval : INTEGER RANGE 0 TO 3; SIGNAL mw_I28reg_nval : INTEGER RANGE 0 TO 3; -- ModuleWare signal declarations(v1.7) for instance 'I30' of 'clkdiv' SIGNAL mw_I30reg_cval : INTEGER RANGE 0 TO 3; SIGNAL mw_I30reg_nval : INTEGER RANGE 0 TO 3; -- ModuleWare signal declarations(v1.7) for instance 'I31' of 'clkdiv' SIGNAL mw_I31reg_cval : INTEGER RANGE 0 TO 1; SIGNAL mw_I31reg_nval : INTEGER RANGE 0 TO 1; -- ModuleWare signal declarations(v1.7) for instance 'I32' of 'clkdiv' SIGNAL mw_I32reg_cval : INTEGER RANGE 0 TO 1; SIGNAL mw_I32reg_nval : INTEGER RANGE 0 TO 1; -- ModuleWare signal declarations(v1.7) for instance 'I33' of 'clkdiv' SIGNAL mw_I33reg_cval : INTEGER RANGE 0 TO 1; SIGNAL mw_I33reg_nval : INTEGER RANGE 0 TO 1; -- ModuleWare signal declarations(v1.7) for instance 'I35' of 'clkdiv' SIGNAL mw_I35reg_cval : INTEGER RANGE 0 TO 1; SIGNAL mw_I35reg_nval : INTEGER RANGE 0 TO 1; -- Component Declarations COMPONENT ADC_read_machn_top PORT ( BUSY : IN std_logic ; CLOCK : IN std_logic ; DATAIN : IN std_logic_vector (7 DOWNTO 0); DSP_CS_n : IN std_logic ; DSP_STRB_n : IN std_logic ; RESET : IN std_logic ; A0 : OUT std_logic ; A1 : OUT std_logic ; AD_CS_n : OUT std_logic ; DATAOUT : OUT std_logic_vector (7 DOWNTO 0); SHIFT_DATA : OUT std_logic ); END COMPONENT; COMPONENT BUF_8_in PORT ( di0 : IN std_logic; di1 : IN std_logic; di2 : IN std_logic; di3 : IN std_logic; di4 : IN std_logic; di5 : IN std_logic; di6 : IN std_logic; di7 : IN std_logic; do : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT; COMPONENT BUF_8_out PORT ( din : IN STD_LOGIC_VECTOR (7 DOWNTO 0); do0 : OUT std_logic; do1 : OUT std_logic; do2 : OUT std_logic; do3 : OUT std_logic; do4 : OUT std_logic; do5 : OUT std_logic; do6 : OUT std_logic; do7 : OUT std_logic ); END COMPONENT; COMPONENT CLOCK_500HZ PORT ( CLK36MHZ : IN std_logic; RESET : IN std_logic; CLK500HZ : BUFFER std_logic ); END COMPONENT; COMPONENT DSPRESET PORT ( CLOCK : IN STD_LOGIC; DSP_RST_STRB : IN STD_LOGIC; DSPRST : OUT STD_LOGIC ); END COMPONENT; COMPONENT DSP_TRIGGER PORT ( AUTOZERO : IN std_logic ; AUTOZERO_ALEVEL : IN std_logic ; AUTOZERO_EN : IN std_logic ; CHARTMARK : IN std_logic ; CHARTMARK_ALEVEL : IN std_logic ; CHARTMARK_EN : IN std_logic ; CPU2000 : IN std_logic ; CPU2000_ALEVEL : IN std_logic ; CPU2000_EN : IN std_logic ; INJECTSTART : IN std_logic ; INJECTSTART_ALEVEL : IN std_logic ; INJECTSTART_EN : IN std_logic ; LAMPONOFF : IN std_logic ; LAMPONOFF_ALEVEL : IN std_logic ; LAMPONOFF_EN : IN std_logic ; EXT_INT_IO_6_DSP : OUT std_logic ); END COMPONENT; COMPONENT FILTER_WHEEL_3977 PORT ( CLOCK : IN STD_LOGIC; FILTER_EN_n : IN STD_LOGIC; FILTER_HOLD_n : IN STD_LOGIC; RESET : IN STD_LOGIC; TPUINPUTS : IN STD_LOGIC_VECTOR (3 DOWNTO 0); FLTR_WHL_DIR : OUT STD_LOGIC; FLTR_WHL_EN : OUT STD_LOGIC; FLTR_WHL_HOLD : OUT STD_LOGIC; FLTR_WHL_RST : OUT STD_LOGIC; FLTR_WHL_STEP : OUT STD_LOGIC ); END COMPONENT; COMPONENT HOSTPORT PORT ( ADR1 : IN std_logic ; ADR2 : IN std_logic ; ADR3 : IN std_logic ; CLK : IN std_logic ; CS9_n : IN std_logic ; HINT_DSP_n : IN std_logic ; HRDY_DSP_n : IN std_logic ; R_W : IN std_logic ; BCS9_n : OUT std_logic ; DSACK1 : OUT std_logic ; HCNTL0_DSP : OUT std_logic ; HCNTL1_DSP : OUT std_logic ; HHWIL_DSP : OUT std_logic ; IRQ5 : OUT std_logic ); END COMPONENT; COMPONENT MEM_MAP_REG PORT ( ADD10 : IN STD_LOGIC; CLOCK : IN STD_LOGIC; PRFRLAD : IN STD_LOGIC_VECTOR (5 DOWNTO 0); RESET : IN STD_LOGIC; R_REG_00008 : IN STD_LOGIC_VECTOR (7 DOWNTO 0); R_REG_00009 : IN STD_LOGIC_VECTOR (7 DOWNTO 0); R_REG_0002A : IN STD_LOGIC_VECTOR (7 DOWNTO 0); R_REG_0002B : IN STD_LOGIC_VECTOR (7 DOWNTO 0); R_REG_0002C : IN STD_LOGIC_VECTOR (7 DOWNTO 0); R_REG_0002E : IN STD_LOGIC_VECTOR (7 DOWNTO 0); R_REG_0002F : IN STD_LOGIC_VECTOR (7 DOWNTO 0); R_REG_00030 : IN STD_LOGIC_VECTOR (7 DOWNTO 0); R_STRB : IN STD_LOGIC; W_STRB : IN STD_LOGIC; BCS5_n : OUT STD_LOGIC; STRB_W_00002 : OUT STD_LOGIC; STRB_W_00004 : OUT STD_LOGIC; STRB_W_0001A : OUT STD_LOGIC; STRB_W_0001B : OUT STD_LOGIC; W_REG_00005 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); W_REG_00006 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); W_REG_00007 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); W_REG_00010 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); W_REG_00011 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); W_REG_00012 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); W_REG_00015 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); W_REG_00019 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); W_REG_0001C : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); W_REG_0001D : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); W_REG_0001E : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); W_REG_0001F : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); W_REG_00020 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); W_REG_00021 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); W_REG_00022 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); W_REG_00023 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); W_REG_00024 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); W_REG_00025 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); W_REG_0003A : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); W_REG_0003B : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); W_REG_0003C : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); W_REG_0003D : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); DATA : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT; COMPONENT NEWDAC1220 PORT ( CLOCK : IN std_logic; PAR_DATA : IN std_logic_vector (31 DOWNTO 0); RESET : IN std_logic; START_BIT : IN std_logic; START_STRB : IN std_logic; CS : OUT std_logic; SCLK : OUT std_logic; SDO : OUT std_logic ); END COMPONENT; COMPONENT PWM_CNTRL PORT ( CNT_CLOCK : IN STD_LOGIC; DATARDY : IN STD_LOGIC; PWM_DCYCLE_CNT : IN STD_LOGIC_VECTOR (15 DOWNTO 0); PWM_FREQ_CNT : IN STD_LOGIC_VECTOR (15 DOWNTO 0); RESET : IN STD_LOGIC; SYSCLOCK : IN STD_LOGIC; TRI_REG : IN STD_LOGIC; PWMOUT : OUT STD_LOGIC ); END COMPONENT; COMPONENT QSPI PORT ( BQSPI_DSP_DATA2CPU : IN std_logic ; BQSPI_PER_DATA2CPU : IN std_logic ; BQSPI_TEMP_DATA2CPU : IN std_logic ; PCS_n : IN std_logic_vector (2 DOWNTO 0); PCS_n_bit3 : IN std_logic ; QSPI_CLK : IN std_logic ; QSPI_CS_EN : IN std_logic ; QSPI_DO : IN std_logic ; BQSPI_CLK : OUT std_logic ; BQSPI_CLK_TEMP : OUT std_logic ; BQSPI_DOUT : OUT std_logic ; BQSPI_DOUT_TEMP : OUT std_logic ; BQSPI_DSP_CS_n : OUT std_logic ; BQSPI_PER_CS_n : OUT std_logic ; BQSPI_TEMP_CS_n : OUT std_logic ; QSPI_DI_n : OUT std_logic ); END COMPONENT; COMPONENT RD_WR_STROBE PORT ( CLOCK : IN std_logic ; CS_n : IN std_logic ; RD_WR : IN std_logic ; RESET : IN std_logic ; CS_STRB_n : OUT std_logic ; R_STROBE : OUT std_logic ; W_STROBE : OUT std_logic ); END COMPONENT; COMPONENT SPI_CNTRL PORT ( CLOCK : IN STD_LOGIC := '0'; DATA_FROM_AD : IN STD_LOGIC; DATA_RDY : IN STD_LOGIC; RESET : IN STD_LOGIC; SYSCLOCK : IN STD_LOGIC := '0'; CS_n : OUT STD_LOGIC; DATA2AD : OUT STD_LOGIC; DATA_CH0 : OUT STD_LOGIC_VECTOR (23 DOWNTO 0); DATA_CH1 : OUT STD_LOGIC_VECTOR (23 DOWNTO 0); DATA_CH2 : OUT STD_LOGIC_VECTOR (23 DOWNTO 0); DATA_RDY_SYNC : OUT STD_LOGIC; SCLK : OUT STD_LOGIC ); END COMPONENT; COMPONENT refmachine PORT ( AD_BUSY : IN STD_LOGIC; AD_SPI_DO : IN STD_LOGIC; CLOCK : IN STD_LOGIC; DEBUG_MODE : IN STD_LOGIC; DSP_SPI_CS : IN STD_LOGIC; DSP_SPI_SCLK : IN STD_LOGIC; REF_START_EXP : IN STD_LOGIC; RESET : IN STD_LOGIC; AD_SPI_CS : OUT STD_LOGIC; AD_SPI_SCLK : OUT STD_LOGIC; DSP_SPI_DI : OUT STD_LOGIC; START_REF_DSP : OUT STD_LOGIC ); END COMPONENT; -- Optional embedded configurations -- pragma synthesis_off FOR ALL : ADC_read_machn_top USE ENTITY PERSONALITY_FPGA.ADC_read_machn_top; FOR ALL : BUF_8_in USE ENTITY PERSONALITY_FPGA.BUF_8_in; FOR ALL : BUF_8_out USE ENTITY PERSONALITY_FPGA.BUF_8_out; FOR ALL : CLOCK_500HZ USE ENTITY PERSONALITY_FPGA.CLOCK_500HZ; FOR ALL : DSPRESET USE ENTITY PERSONALITY_FPGA.DSPRESET; FOR ALL : DSP_TRIGGER USE ENTITY PERSONALITY_FPGA.DSP_TRIGGER; FOR ALL : FILTER_WHEEL_3977 USE ENTITY PERSONALITY_FPGA.FILTER_WHEEL_3977; FOR ALL : HOSTPORT USE ENTITY PERSONALITY_FPGA.HOSTPORT; FOR ALL : MEM_MAP_REG USE ENTITY PERSONALITY_FPGA.MEM_MAP_REG; FOR ALL : NEWDAC1220 USE ENTITY PERSONALITY_FPGA.NEWDAC1220; FOR ALL : PWM_CNTRL USE ENTITY PERSONALITY_FPGA.PWM_CNTRL; FOR ALL : QSPI USE ENTITY PERSONALITY_FPGA.QSPI; FOR ALL : RD_WR_STROBE USE ENTITY PERSONALITY_FPGA.RD_WR_STROBE; FOR ALL : SPI_CNTRL USE ENTITY PERSONALITY_FPGA.SPI_CNTRL; FOR ALL : refmachine USE ENTITY PERSONALITY_FPGA.refmachine; -- pragma synthesis_on BEGIN -- ModuleWare code(v1.7) for instance 'I12' of 'adff' q <= mw_I12reg_cval; i12seq_proc: PROCESS (CLOCK18MHZ)BEGIN IF (CLOCK18MHZ'EVENT AND CLOCK18MHZ='1') THEN mw_I12reg_cval <= PDABUSY; END IF; END PROCESS i12seq_proc; -- ModuleWare code(v1.7) for instance 'I16' of 'adff' BUSY <= mw_I16reg_cval; i16seq_proc: PROCESS (CLOCK18MHZ)BEGIN IF (CLOCK18MHZ'EVENT AND CLOCK18MHZ='1') THEN mw_I16reg_cval <= q; END IF; END PROCESS i16seq_proc; -- ModuleWare code(v1.7) for instance 'I29' of 'and' B_DATA_CS_n <= CS8_n AND CS4_n AND dout3; -- ModuleWare code(v1.7) for instance 'I36' of 'and' dout4 <= CS4_n AND CS8_n; -- ModuleWare code(v1.7) for instance 'I43' of 'and' DEBUG_MODE <= do0 AND NOT(do1) AND do2 AND NOT(do3); -- ModuleWare code(v1.7) for instance 'I34' of 'buff' R_W_BUF <= RD_WR; -- ModuleWare code(v1.7) for instance 'I37' of 'buff' EXT_INT_IO_4_DSP <= EOS; -- ModuleWare code(v1.7) for instance 'I39' of 'buff' SEL_EN <= TIN0_DSP; -- ModuleWare code(v1.7) for instance 'I41' of 'buff' UB_GPU <= CS4_n; -- ModuleWare code(v1.7) for instance 'I44' of 'buff' START_PDA_DSP <= TOUT1_DSP; -- ModuleWare code(v1.7) for instance 'I47' of 'buff' BBCS9_n <= CS9_n; -- ModuleWare code(v1.7) for instance 'I48' of 'buff' FAN_PWM <= HEATER_PWM_internal; -- ModuleWare code(v1.7) for instance 'I52' of 'buff' LB_GPU <= CS8_n; -- ModuleWare code(v1.7) for instance 'I22' of 'clkdiv' i22drive_proc: PROCESS (mw_I22reg_cval) BEGIN IF (mw_I22reg_cval >= 1) THEN CLOCK18MHZ <= '1'; ELSE CLOCK18MHZ <= '0'; END IF; END PROCESS i22drive_proc; i22clk_in_proc: PROCESS (CLOCK, RESET) BEGIN IF (RESET = '1' OR RESET = 'H') THEN mw_I22reg_cval <= 0; ELSIF (CLOCK'EVENT AND CLOCK='1') THEN mw_I22reg_cval <= mw_I22reg_nval; END IF; END PROCESS i22clk_in_proc; i22combo_proc: PROCESS (mw_I22reg_cval) BEGIN IF (mw_I22reg_cval = 1) THEN mw_I22reg_nval <= 0; ELSE mw_I22reg_nval <= mw_I22reg_cval + 1; END IF; END PROCESS i22combo_proc; -- ModuleWare code(v1.7) for instance 'I28' of 'clkdiv' i28drive_proc: PROCESS (mw_I28reg_cval) BEGIN IF (mw_I28reg_cval >= 2) THEN CLOCK281KHZ <= '1'; ELSE CLOCK281KHZ <= '0'; END IF; END PROCESS i28drive_proc; i28clk_in_proc: PROCESS (CLOCK1125KHZ, RESET) BEGIN IF (RESET = '1' OR RESET = 'H') THEN mw_I28reg_cval <= 0; ELSIF (CLOCK1125KHZ'EVENT AND CLOCK1125KHZ='1') THEN mw_I28reg_cval <= mw_I28reg_nval; END IF; END PROCESS i28clk_in_proc; i28combo_proc: PROCESS (mw_I28reg_cval) BEGIN IF (mw_I28reg_cval = 3) THEN mw_I28reg_nval <= 0; ELSE mw_I28reg_nval <= mw_I28reg_cval + 1; END IF; END PROCESS i28combo_proc; -- ModuleWare code(v1.7) for instance 'I30' of 'clkdiv' i30drive_proc: PROCESS (mw_I30reg_cval) BEGIN IF (mw_I30reg_cval >= 2) THEN CLOCK70KHZ <= '1'; ELSE CLOCK70KHZ <= '0'; END IF; END PROCESS i30drive_proc; i30clk_in_proc: PROCESS (CLOCK281KHZ, RESET) BEGIN IF (RESET = '1' OR RESET = 'H') THEN mw_I30reg_cval <= 0; ELSIF (CLOCK281KHZ'EVENT AND CLOCK281KHZ='1') THEN mw_I30reg_cval <= mw_I30reg_nval; END IF; END PROCESS i30clk_in_proc; i30combo_proc: PROCESS (mw_I30reg_cval) BEGIN IF (mw_I30reg_cval = 3) THEN mw_I30reg_nval <= 0; ELSE mw_I30reg_nval <= mw_I30reg_cval + 1; END IF; END PROCESS i30combo_proc; -- ModuleWare code(v1.7) for instance 'I31' of 'clkdiv' i31drive_proc: PROCESS (mw_I31reg_cval) BEGIN IF (mw_I31reg_cval >= 1) THEN CLOCK1125KHZ <= '1'; ELSE CLOCK1125KHZ <= '0'; END IF; END PROCESS i31drive_proc; i31clk_in_proc: PROCESS (PER_AD_CLK_internal, RESET) BEGIN IF (RESET = '1' OR RESET = 'H') THEN mw_I31reg_cval <= 0; ELSIF (PER_AD_CLK_internal'EVENT AND PER_AD_CLK_internal='1') THEN mw_I31reg_cval <= mw_I31reg_nval; END IF; END PROCESS i31clk_in_proc; i31combo_proc: PROCESS (mw_I31reg_cval) BEGIN IF (mw_I31reg_cval = 1) THEN mw_I31reg_nval <= 0; ELSE mw_I31reg_nval <= mw_I31reg_cval + 1; END IF; END PROCESS i31combo_proc; -- ModuleWare code(v1.7) for instance 'I32' of 'clkdiv' i32drive_proc: PROCESS (mw_I32reg_cval) BEGIN IF (mw_I32reg_cval >= 1) THEN CLOCK9MHZ <= '1'; ELSE CLOCK9MHZ <= '0'; END IF; END PROCESS i32drive_proc; i32clk_in_proc: PROCESS (CLOCK18MHZ, RESET) BEGIN IF (RESET = '1' OR RESET = 'H') THEN mw_I32reg_cval <= 0; ELSIF (CLOCK18MHZ'EVENT AND CLOCK18MHZ='1') THEN mw_I32reg_cval <= mw_I32reg_nval; END IF; END PROCESS i32clk_in_proc; i32combo_proc: PROCESS (mw_I32reg_cval) BEGIN IF (mw_I32reg_cval = 1) THEN mw_I32reg_nval <= 0; ELSE mw_I32reg_nval <= mw_I32reg_cval + 1; END IF; END PROCESS i32combo_proc; -- ModuleWare code(v1.7) for instance 'I33' of 'clkdiv' i33drive_proc: PROCESS (mw_I33reg_cval) BEGIN IF (mw_I33reg_cval >= 1) THEN CLOCK4_5MHZ <= '1'; ELSE CLOCK4_5MHZ <= '0'; END IF; END PROCESS i33drive_proc; i33clk_in_proc: PROCESS (CLOCK9MHZ, RESET) BEGIN IF (RESET = '1' OR RESET = 'H') THEN mw_I33reg_cval <= 0; ELSIF (CLOCK9MHZ'EVENT AND CLOCK9MHZ='1') THEN mw_I33reg_cval <= mw_I33reg_nval; END IF; END PROCESS i33clk_in_proc; i33combo_proc: PROCESS (mw_I33reg_cval) BEGIN IF (mw_I33reg_cval = 1) THEN mw_I33reg_nval <= 0; ELSE mw_I33reg_nval <= mw_I33reg_cval + 1; END IF; END PROCESS i33combo_proc; -- ModuleWare code(v1.7) for instance 'I35' of 'clkdiv' i35drive_proc: PROCESS (mw_I35reg_cval) BEGIN IF (mw_I35reg_cval >= 1) THEN PER_AD_CLK_internal <= '1'; ELSE PER_AD_CLK_internal <= '0'; END IF; END PROCESS i35drive_proc; i35clk_in_proc: PROCESS (CLOCK4_5MHZ, RESET) BEGIN IF (RESET = '1' OR RESET = 'H') THEN mw_I35reg_cval <= 0; ELSIF (CLOCK4_5MHZ'EVENT AND CLOCK4_5MHZ='1') THEN mw_I35reg_cval <= mw_I35reg_nval; END IF; END PROCESS i35clk_in_proc; i35combo_proc: PROCESS (mw_I35reg_cval) BEGIN IF (mw_I35reg_cval = 1) THEN mw_I35reg_nval <= 0; ELSE mw_I35reg_nval <= mw_I35reg_cval + 1; END IF; END PROCESS i35combo_proc; -- ModuleWare code(v1.7) for instance 'I7' of 'inv' RESET <= NOT(RESET_n); -- ModuleWare code(v1.7) for instance 'I15' of 'inv' EXT_INT_IO_5_DSP <= NOT(BUSY); -- ModuleWare code(v1.7) for instance 'I24' of 'inv' TPUBUS8 <= NOT(DATA_RDY_SYNC); -- ModuleWare code(v1.7) for instance 'I45' of 'inv' W_R_BUF <= NOT(RD_WR); -- ModuleWare code(v1.7) for instance 'I49' of 'inv' dout2 <= NOT(dout1); -- ModuleWare code(v1.7) for instance 'I53' of 'inv' LAMP_ON <= NOT(do4); -- ModuleWare code(v1.7) for instance 'I56' of 'inv' TRI_REG <= NOT(do5); -- ModuleWare code(v1.7) for instance 'I57' of 'inv' DISABLE_THERM <= NOT(do6); -- ModuleWare code(v1.7) for instance 'I26' of 'or' PIDRST <= DISABLE_THERM OR RESET; -- ModuleWare code(v1.7) for instance 'I51' of 'or' dout3 <= CS5_n OR BCS5_n; -- ModuleWare code(v1.7) for instance 'I9' of 'vdd' dout <= '1'; -- ModuleWare code(v1.7) for instance 'I50' of 'vdd' dout1 <= '1'; -- Instance port mappings. I14 : ADC_read_machn_top PORT MAP ( BUSY => BUSY, CLOCK => CLOCK4_5MHZ, DATAIN => EMIFDATA_IN, DSP_CS_n => CE_ADC_PAR_READ_n, DSP_STRB_n => COLUMN_STRB_n, RESET => RESET, A0 => A0_BYTE, A1 => A1_BYTE, AD_CS_n => READ_PDA_n, DATAOUT => EMIFDATA_OUT, SHIFT_DATA => GP2 ); I1 : BUF_8_in PORT MAP ( do => R_REG_00008, di0 => LEAK_DET_PRESENT_n, di1 => dout, di2 => LAMP_LIT_n, di3 => dout, di4 => FUSE_24V, di5 => RMTVCC_FUSE, di6 => FUSE_15V, di7 => dout ); I46 : BUF_8_in PORT MAP ( do => R_REG_00009, di0 => dout2, di1 => dout2, di2 => dout, di3 => dout, di4 => dout, di5 => dout2, di6 => dout, di7 => dout2 ); I2 : BUF_8_out PORT MAP ( din => W_REG_00005, do0 => STAT_GRN, do1 => STAT_RED, do2 => OPEN, do3 => OPEN, do4 => EVENT_OUT1, do5 => EVENT_OUT2, do6 => OPEN, do7 => OPEN ); I5 : BUF_8_out PORT MAP ( din => W_REG_00006, do0 => FILTER_EN_n, do1 => FILTER_HOLD_n, do2 => OPEN, do3 => OPEN, do4 => OPEN, do5 => OPEN, do6 => OPEN, do7 => OPEN ); I6 : BUF_8_out PORT MAP ( din => W_REG_00007, do0 => OPEN, do1 => do4, do2 => OPEN, do3 => OPEN, do4 => OPEN, do5 => OPEN, do6 => OPEN, do7 => OPEN ); I18 : BUF_8_out PORT MAP ( din => W_REG_00010, do0 => AUTOZERO_ALEVEL, do1 => CHARTMARK_ALEVEL, do2 => OPEN, do3 => INJECTSTART_ALEVEL, do4 => LAMPONOFF_ALEVEL, do5 => CPU2000_ALEVEL, do6 => OPEN, do7 => OPEN ); I19 : BUF_8_out PORT MAP ( din => W_REG_00011, do0 => AUTOZERO_EN, do1 => CHARTMARK_EN, do2 => OPEN, do3 => INJECTSTART_EN, do4 => LAMPONOFF_EN, do5 => CPU2000_EN, do6 => OPEN, do7 => OPEN ); I23 : BUF_8_out PORT MAP ( din => W_REG_00012, do0 => SPI_ENABLE, do1 => OPEN, do2 => OPEN, do3 => OPEN, do4 => OPEN, do5 => OPEN, do6 => OPEN, do7 => OPEN ); I27 : BUF_8_out PORT MAP ( din => W_REG_00015, do0 => do0, do1 => do1, do2 => do2, do3 => do3, do4 => OPEN, do5 => OPEN, do6 => OPEN, do7 => OPEN ); I38 : BUF_8_out PORT MAP ( din => W_REG_00019, do0 => do5, do1 => do6, do2 => OPEN, do3 => OPEN, do4 => OPEN, do5 => OPEN, do6 => OPEN, do7 => OPEN ); I13 : CLOCK_500HZ PORT MAP ( RESET => RESET, CLK36MHZ => CLOCK, CLK500HZ => EXT_INT_IO_7_DSP_internal ); I42 : DSPRESET PORT MAP ( CLOCK => CLOCK9MHZ, DSP_RST_STRB => DSP_RST_STRB, DSPRST => DSP_SOFTWARE_RST_n ); I25 : DSP_TRIGGER PORT MAP ( AUTOZERO => AUTOZERO, AUTOZERO_ALEVEL => AUTOZERO_ALEVEL, AUTOZERO_EN => AUTOZERO_EN, CHARTMARK => CHARTMARK, CHARTMARK_ALEVEL => CHARTMARK_ALEVEL, CHARTMARK_EN => CHARTMARK_EN, CPU2000 => TPUBUS7, CPU2000_ALEVEL => CPU2000_ALEVEL, CPU2000_EN => CPU2000_EN, INJECTSTART => INJECTSTART, INJECTSTART_ALEVEL => INJECTSTART_ALEVEL, INJECTSTART_EN => INJECTSTART_EN, LAMPONOFF => LAMPONOFF, LAMPONOFF_ALEVEL => LAMPONOFF_ALEVEL, LAMPONOFF_EN => LAMPONOFF_EN, EXT_INT_IO_6_DSP => EXT_INT_IO_6_DSP ); I40 : FILTER_WHEEL_3977 PORT MAP ( CLOCK => CLOCK18MHZ, RESET => RESET, TPUINPUTS => TPUBUS(12 DOWNTO 9), FILTER_HOLD_n => FILTER_HOLD_n, FILTER_EN_n => FILTER_EN_n, FLTR_WHL_HOLD => FLTR_WHL_HOLD, FLTR_WHL_EN => FLTR_WHL_EN, FLTR_WHL_RST => FLTR_WHL_RST, FLTR_WHL_DIR => FLTR_WHL_DIR, FLTR_WHL_STEP => FLTR_WHL_STEP ); I21 : HOSTPORT PORT MAP ( ADR1 => ADR(1), ADR2 => ADR(2), ADR3 => ADR(3), CLK => CLOCK, CS9_n => CS9_n, HINT_DSP_n => HINT_DSP_n, HRDY_DSP_n => HRDY_DSP_n, R_W => RD_WR, BCS9_n => BCS9_n, DSACK1 => DSACK1, HCNTL0_DSP => HCNTL0_DSP, HCNTL1_DSP => HCNTL1_DSP, HHWIL_DSP => HHWIL_DSP, IRQ5 => IRQ5 ); I3 : MEM_MAP_REG PORT MAP ( RESET => RESET, CLOCK => CLOCK18MHZ, PRFRLAD => ADR, ADD10 => ADD10, W_STRB => W_STROBE, R_STRB => R_STROBE, DATA => DATA, BCS5_n => BCS5_n, STRB_W_00002 => DSP_RST_STRB, STRB_W_00004 => LED_LOOP_STRB, W_REG_00005 => W_REG_00005, W_REG_00006 => W_REG_00006, W_REG_00007 => W_REG_00007, R_REG_00008 => R_REG_00008, R_REG_00009 => R_REG_00009, W_REG_00010 => W_REG_00010, W_REG_00011 => W_REG_00011, W_REG_00012 => W_REG_00012, W_REG_00015 => W_REG_00015, W_REG_00019 => W_REG_00019, STRB_W_0001A => FLTR_STRB, STRB_W_0001B => DACSENDCMD, W_REG_0001C => OPEN, W_REG_0001D => DAC1_DATA(23 DOWNTO 16), W_REG_0001E => DAC1_DATA(15 DOWNTO 8), W_REG_0001F => DAC1_DATA(7 DOWNTO 0), W_REG_00020 => OPEN, W_REG_00021 => DAC2_DATA(23 DOWNTO 16), W_REG_00022 => DAC2_DATA(15 DOWNTO 8), W_REG_00023 => DAC2_DATA(7 DOWNTO 0), W_REG_00024 => DAC1_DATA(31 DOWNTO 24), W_REG_00025 => DAC2_DATA(31 DOWNTO 24), R_REG_0002A => DATA_CH0(23 DOWNTO 16), R_REG_0002B => DATA_CH0(15 DOWNTO 8), R_REG_0002C => DATA_CH0(7 DOWNTO 0), R_REG_0002E => DATA_CH1(23 DOWNTO 16), R_REG_0002F => DATA_CH1(15 DOWNTO 8), R_REG_00030 => DATA_CH1(7 DOWNTO 0), W_REG_0003A => PWM2_FREQ_CNT(15 DOWNTO 8), W_REG_0003B => PWM2_FREQ_CNT(7 DOWNTO 0), W_REG_0003C => PWM2_DCYCLE_CNT(15 DOWNTO 8), W_REG_0003D => PWM2_DCYCLE_CNT(7 DOWNTO 0) ); I10 : NEWDAC1220 PORT MAP ( CLOCK => CLOCK70KHZ, PAR_DATA => DAC2_DATA, RESET => RESET, START_BIT => DATA(10), START_STRB => DACSENDCMD, CS => CS_DAC2_n, SCLK => SCLK_DAC_2, SDO => SDIO_DAC_2 ); I17 : NEWDAC1220 PORT MAP ( CLOCK => CLOCK70KHZ, PAR_DATA => DAC1_DATA, RESET => RESET, START_BIT => DATA(8), START_STRB => DACSENDCMD, CS => CS_DAC1_n, SCLK => SCLK_DAC_1, SDO => SDIO_DAC_1 ); I8 : PWM_CNTRL PORT MAP ( SYSCLOCK => CLOCK18MHZ, CNT_CLOCK => CLOCK1125KHZ, RESET => PIDRST, TRI_REG => DISABLE_THERM, DATARDY => DATA_RDY_SYNC, PWMOUT => HEATER_PWM_internal, PWM_FREQ_CNT => PWM2_FREQ_CNT, PWM_DCYCLE_CNT => PWM2_DCYCLE_CNT ); I0 : QSPI PORT MAP ( BQSPI_DSP_DATA2CPU => BQSPI_DSP_DATA2CPU, BQSPI_PER_DATA2CPU => BQSPI_PER_DATA2CPU, BQSPI_TEMP_DATA2CPU => BQSPI_TEMP_DATA2CPU, PCS_n => PCS_n, PCS_n_bit3 => PCS_n_bit3, QSPI_CLK => QSPI_CLK, QSPI_CS_EN => SPI_ENABLE, QSPI_DO => QSPI_DO, BQSPI_CLK => BQSPI_CLK, BQSPI_CLK_TEMP => BQSPI_CLK_TEMP, BQSPI_DOUT => BQSPI_DOUT, BQSPI_DOUT_TEMP => BQSPI_DOUT_TEMP, BQSPI_DSP_CS_n => BQSPI_DSP_CS_n, BQSPI_PER_CS_n => BQSPI_PER_CS_n, BQSPI_TEMP_CS_n => BQSPI_TEMP_CS_n, QSPI_DI_n => QSPI_DI_n ); I11 : RD_WR_STROBE PORT MAP ( CLOCK => CLOCK18MHZ, CS_n => CS5_n, RD_WR => RD_WR, RESET => RESET, CS_STRB_n => OPEN, R_STROBE => R_STROBE, W_STROBE => W_STROBE ); I54 : RD_WR_STROBE PORT MAP ( CLOCK => CLOCK, CS_n => dout4, RD_WR => RD_WR, RESET => RESET, CS_STRB_n => MEM_CS_n, R_STROBE => OPEN, W_STROBE => OPEN ); I4 : SPI_CNTRL PORT MAP ( SYSCLOCK => CLOCK18MHZ, CLOCK => CLOCK281KHZ, RESET => PIDRST, SCLK => SCLK_THERM, CS_n => CS_THERM_n, DATA_FROM_AD => DOUT_THERM, DATA2AD => DIN_THERM, DATA_RDY => DRDY_THERM_n, DATA_RDY_SYNC => DATA_RDY_SYNC, DATA_CH0 => DATA_CH0, DATA_CH1 => DATA_CH1, DATA_CH2 => OPEN ); I20 : refmachine PORT MAP ( CLOCK => CLOCK, RESET => RESET, AD_SPI_DO => REFSDATA, AD_BUSY => REFBUSY, REF_START_EXP => TOUT0_DSP, DSP_SPI_SCLK => BSPI_CLKX0, DSP_SPI_CS => BSPI_FSX0, DEBUG_MODE => DEBUG_MODE, START_REF_DSP => START_REF_DSP, AD_SPI_SCLK => REFSCLK, AD_SPI_CS => REFCS_n, DSP_SPI_DI => BSPI_DR0 ); -- Implicit buffered output assignments EXT_INT_IO_7_DSP <= EXT_INT_IO_7_DSP_internal; PER_AD_CLK <= PER_AD_CLK_internal; HEATER_PWM <= HEATER_PWM_internal; END struct;