# //  ModelSim SE 5.8c Mar 01 2004 
# //
# //  Copyright Model Technology, a Mentor Graphics Corporation company, 2004
# //                         All Rights Reserved.
# //                   UNPUBLISHED, LICENSED SOFTWARE.
# //         CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
# //        PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS.
# //
# vsim -L PERSONALITY_FPGA -l transcript.txt -i -multisource_delay latest -t 10ns +typdelays -foreign {hdsInit C:/ECAD/FPGA_ADV/Hds/resources/downstream/modelsim/ModelSim_32Bit.dll} -pli C:/ECAD/FPGA_ADV/Hds/resources/downstream/modelsim/ModelSim_32Bit.dll PERSONALITY_FPGA.ADC_read_machn_top_tb(struct) 
# Loading C:/ECAD/FPGA_ADV/Hds/resources/downstream/modelsim/ModelSim_32Bit.dll
# Loading C:\ECAD\FPGA_ADV\Modeltech\win32/../std.standard
# Loading C:\ECAD\FPGA_ADV\Modeltech\win32/../ieee.std_logic_1164(body)
# Loading C:\ECAD\FPGA_ADV\Modeltech\win32/../ieee.std_logic_arith(body)
# Loading C:\hds_projects\2998_Per_FPGA_RevC_Ver47(working)\361000242_RevA/PERSONALITY_FPGA/work/.adc_read_machn_top_tb(struct)
# Loading C:\hds_projects\2998_Per_FPGA_RevC_Ver47(working)\361000242_RevA/PERSONALITY_FPGA/work/.adc_read_machn_top(struct)
# Loading C:\hds_projects\2998_Per_FPGA_RevC_Ver47(working)\361000242_RevA/PERSONALITY_FPGA/work/.adc_read_machn_dsp_cntrl(rtl)
# Loading C:\hds_projects\2998_Per_FPGA_RevC_Ver47(working)\361000242_RevA/PERSONALITY_FPGA/work/.adc_read_machn_fpga_cntrl(rtl)
# Loading C:\hds_projects\2998_Per_FPGA_RevC_Ver47(working)\361000242_RevA/PERSONALITY_FPGA/work/.adc_read_machn_top_tester(rtl)
# ** Warning: (vsim-3479) Time unit 'ns' is less than the simulator resolution (10ns).
#    Time: 0 ns  Iteration: 0  Region: /adc_read_machn_top_tb/i1
view wave
# .wave
view signals
# .signals
# ** Warning: (vsim-WLF-5000) Log file vsim.wlf currently in use.
# File in use by: DearyJ  Hostname: DEARY-JUSTIN  ProcessID: 2196
#           Attempting to use alternate file "C:\TEMP\wlft3".
# ** Warning: (vsim-WLF-5001) Could not open log file vsim.wlf.  Using C:\TEMP\wlft3 instead.
run 100us
# Break key hit 
# 0
# Break at C:/hds_projects/2998_Per_FPGA_RevC_Ver47(working)/361000242_RevA/PERSONALITY_FPGA/hdl/ADC_read_machn_top_tester_rtl.vhd line 70
run 100n
# Invalid time value: 100n
run 100ns
# Break key hit 
# Break at C:/hds_projects/2998_Per_FPGA_RevC_Ver47(working)/361000242_RevA/PERSONALITY_FPGA/hdl/ADC_read_machn_top_tester_rtl.vhd line 70
# hds_restart 
restart -force
# Loading C:/ECAD/FPGA_ADV/Hds/resources/downstream/modelsim/ModelSim_32Bit.dll
# Loading C:\hds_projects\2998_Per_FPGA_RevC_Ver47(working)\361000242_RevA/PERSONALITY_FPGA/work.adc_read_machn_top_tb(struct)
# Loading C:\hds_projects\2998_Per_FPGA_RevC_Ver47(working)\361000242_RevA/PERSONALITY_FPGA/work.adc_read_machn_top(struct)
# Loading C:\hds_projects\2998_Per_FPGA_RevC_Ver47(working)\361000242_RevA/PERSONALITY_FPGA/work.adc_read_machn_dsp_cntrl(rtl)
# Loading C:\hds_projects\2998_Per_FPGA_RevC_Ver47(working)\361000242_RevA/PERSONALITY_FPGA/work.adc_read_machn_fpga_cntrl(rtl)
# Loading C:\hds_projects\2998_Per_FPGA_RevC_Ver47(working)\361000242_RevA/PERSONALITY_FPGA/work.adc_read_machn_top_tester(rtl)
# ** Warning: (vsim-WLF-5000) Log file vsim.wlf currently in use.
# File in use by: DearyJ  Hostname: DEARY-JUSTIN  ProcessID: 2196
#           Attempting to use alternate file "C:\TEMP\wlft4".
# ** Warning: (vsim-WLF-5001) Could not open log file vsim.wlf.  Using C:\TEMP\wlft4 instead.
run 100ns
run 100ns
run 1000ns
run 1000ns
run 1000ns
run 1000ns
# 0
# 

run 1000ns
run 1000ns